Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14349912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58273761

1

T2

149057

T3

98

T4

288879

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36214583	1			T2	82353		T3	43		T4	159084
values[0x0]	16771195	1			T2	39389		T3	27		T4	76619
values[0x1]	19637895	1			T2	42282		T3	28		T4	82107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7148235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65475438

1

T2

156574

T3

98

T4

303212

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	294808	1			T2	544		T4	1432		T8	5
valid_sources[0x01]	298676	1			T2	723		T4	1102		T8	1
valid_sources[0x02]	432693	1			T2	708		T4	1186		T8	2
valid_sources[0x03]	287427	1			T2	679		T4	1173		T8	4
valid_sources[0x04]	303131	1			T2	646		T3	2		T4	1415
valid_sources[0x05]	312941	1			T2	621		T3	1		T4	1326
valid_sources[0x06]	306600	1			T2	633		T3	2		T4	1332
valid_sources[0x07]	251987	1			T2	672		T4	1282		T8	1
valid_sources[0x08]	289663	1			T2	686		T4	1231		T8	3
valid_sources[0x09]	286873	1			T2	688		T4	1308		T8	7
valid_sources[0x0a]	280149	1			T2	708		T4	1060		T8	3
valid_sources[0x0b]	274151	1			T2	654		T4	1100		T8	5
valid_sources[0x0c]	299222	1			T2	760		T4	1161		T8	5
valid_sources[0x0d]	289935	1			T2	688		T4	1182		T8	7
valid_sources[0x0e]	303243	1			T2	778		T4	1422		T8	2
valid_sources[0x0f]	339966	1			T2	659		T4	1234		T8	5
valid_sources[0x10]	258355	1			T2	770		T4	969		T8	8
valid_sources[0x11]	267035	1			T2	622		T3	2		T4	1320
valid_sources[0x12]	273692	1			T2	645		T4	1210		T8	6
valid_sources[0x13]	309837	1			T2	728		T4	1338		T8	4
valid_sources[0x14]	277297	1			T2	675		T4	1229		T5	30
valid_sources[0x15]	339380	1			T2	643		T4	1452		T8	1
valid_sources[0x16]	282886	1			T2	674		T4	1259		T8	3
valid_sources[0x17]	308935	1			T2	558		T4	1153		T8	2
valid_sources[0x18]	306807	1			T2	707		T4	1465		T8	3
valid_sources[0x19]	277158	1			T2	643		T4	1088		T8	3
valid_sources[0x1a]	329389	1			T2	687		T3	1		T4	1336
valid_sources[0x1b]	357094	1			T2	614		T4	1202		T8	7
valid_sources[0x1c]	267546	1			T2	567		T4	1300		T8	2
valid_sources[0x1d]	260762	1			T2	573		T4	1436		T8	5
valid_sources[0x1e]	250602	1			T2	684		T3	2		T4	1317
valid_sources[0x1f]	263553	1			T2	571		T4	1341		T8	4
valid_sources[0x20]	319554	1			T2	490		T3	2		T4	1315
valid_sources[0x21]	257522	1			T2	620		T4	1278		T8	3
valid_sources[0x22]	291243	1			T2	544		T3	1		T4	1178
valid_sources[0x23]	321538	1			T2	698		T4	1293		T8	5
valid_sources[0x24]	254229	1			T2	629		T4	1210		T8	7
valid_sources[0x25]	270005	1			T2	759		T4	1209		T8	4
valid_sources[0x26]	298160	1			T2	826		T4	1235		T8	4
valid_sources[0x27]	303338	1			T2	699		T4	1135		T8	2
valid_sources[0x28]	272530	1			T2	629		T4	1031		T8	7
valid_sources[0x29]	290908	1			T2	593		T4	1410		T5	35
valid_sources[0x2a]	301431	1			T2	580		T4	1206		T8	3
valid_sources[0x2b]	264870	1			T2	536		T4	1179		T8	5
valid_sources[0x2c]	267725	1			T2	524		T4	1078		T8	6
valid_sources[0x2d]	254777	1			T2	661		T4	1011		T8	4
valid_sources[0x2e]	306538	1			T2	662		T4	1203		T8	4
valid_sources[0x2f]	289308	1			T2	548		T4	1164		T8	2
valid_sources[0x30]	253940	1			T2	624		T4	1361		T8	1
valid_sources[0x31]	327461	1			T2	580		T4	1131		T8	2
valid_sources[0x32]	320397	1			T2	648		T4	1038		T8	5
valid_sources[0x33]	263613	1			T2	626		T3	2		T4	1157
valid_sources[0x34]	293674	1			T2	768		T3	1		T4	1318
valid_sources[0x35]	317504	1			T2	607		T4	1307		T8	1
valid_sources[0x36]	314120	1			T2	747		T4	1177		T8	2
valid_sources[0x37]	286820	1			T2	583		T3	1		T4	1177
valid_sources[0x38]	286214	1			T2	661		T4	1178		T8	3
valid_sources[0x39]	249041	1			T2	642		T4	1346		T8	7
valid_sources[0x3a]	289726	1			T2	589		T4	1309		T8	3
valid_sources[0x3b]	266116	1			T2	564		T4	1097		T5	12
valid_sources[0x3c]	251230	1			T2	554		T3	1		T4	1015
valid_sources[0x3d]	375624	1			T2	672		T4	1200		T8	3
valid_sources[0x3e]	264175	1			T2	632		T4	1205		T8	2
valid_sources[0x3f]	281023	1			T2	587		T3	1		T4	1281
valid_sources[0x40]	274022	1			T2	660		T4	1237		T5	55
valid_sources[0x41]	267443	1			T2	673		T4	1415		T8	3
valid_sources[0x42]	315771	1			T2	585		T4	1366		T8	5
valid_sources[0x43]	302741	1			T2	699		T3	1		T4	1369
valid_sources[0x44]	252837	1			T2	666		T4	1226		T8	2
valid_sources[0x45]	274423	1			T2	738		T4	1386		T8	3
valid_sources[0x46]	255229	1			T2	577		T3	1		T4	1198
valid_sources[0x47]	274994	1			T2	640		T3	3		T4	1180
valid_sources[0x48]	281290	1			T2	547		T4	1215		T5	57
valid_sources[0x49]	258682	1			T2	671		T4	1184		T6	1115
valid_sources[0x4a]	272356	1			T2	666		T4	1232		T8	3
valid_sources[0x4b]	260996	1			T2	640		T4	1290		T6	902
valid_sources[0x4c]	263306	1			T2	619		T3	3		T4	1064
valid_sources[0x4d]	269135	1			T2	644		T4	1316		T8	4
valid_sources[0x4e]	276789	1			T2	662		T4	1227		T8	5
valid_sources[0x4f]	269816	1			T2	655		T4	1200		T8	5
valid_sources[0x50]	273149	1			T2	640		T4	1217		T8	11
valid_sources[0x51]	330068	1			T2	589		T4	1166		T8	4
valid_sources[0x52]	272191	1			T2	753		T4	1299		T8	3
valid_sources[0x53]	348221	1			T2	555		T4	1085		T8	4
valid_sources[0x54]	251672	1			T2	681		T4	1152		T8	1
valid_sources[0x55]	248028	1			T2	616		T4	1184		T8	6
valid_sources[0x56]	250856	1			T2	634		T4	1252		T8	5
valid_sources[0x57]	256111	1			T2	582		T4	960		T5	93
valid_sources[0x58]	258765	1			T2	774		T4	1493		T8	4
valid_sources[0x59]	305762	1			T2	625		T4	1254		T8	1
valid_sources[0x5a]	296758	1			T2	665		T4	1376		T8	3
valid_sources[0x5b]	284240	1			T2	641		T3	1		T4	1437
valid_sources[0x5c]	265901	1			T2	682		T3	2		T4	1325
valid_sources[0x5d]	273611	1			T2	734		T4	1324		T8	3
valid_sources[0x5e]	255779	1			T2	674		T3	4		T4	1436
valid_sources[0x5f]	254001	1			T2	607		T4	1137		T8	4
valid_sources[0x60]	293327	1			T2	626		T4	1335		T8	3
valid_sources[0x61]	282785	1			T2	592		T4	1273		T8	6
valid_sources[0x62]	257896	1			T2	649		T4	1096		T5	30
valid_sources[0x63]	258144	1			T2	604		T4	1292		T8	1
valid_sources[0x64]	250711	1			T2	655		T3	2		T4	1204
valid_sources[0x65]	311408	1			T2	657		T4	1020		T8	3
valid_sources[0x66]	267859	1			T2	646		T4	915		T8	7
valid_sources[0x67]	258740	1			T2	617		T4	1233		T8	2
valid_sources[0x68]	252604	1			T2	543		T3	2		T4	1166
valid_sources[0x69]	250366	1			T2	659		T4	1071		T8	2
valid_sources[0x6a]	254301	1			T2	613		T4	1332		T8	6
valid_sources[0x6b]	287257	1			T2	599		T4	1254		T8	4
valid_sources[0x6c]	254482	1			T2	834		T4	1300		T8	2
valid_sources[0x6d]	298439	1			T2	595		T4	1421		T8	7
valid_sources[0x6e]	253497	1			T2	657		T4	1095		T5	50
valid_sources[0x6f]	318859	1			T2	713		T4	1337		T5	76
valid_sources[0x70]	276914	1			T2	606		T4	1443		T8	3
valid_sources[0x71]	259499	1			T2	596		T3	1		T4	1217
valid_sources[0x72]	318517	1			T2	568		T3	2		T4	1320
valid_sources[0x73]	282963	1			T2	633		T4	1253		T8	8
valid_sources[0x74]	259661	1			T2	637		T3	2		T4	1196
valid_sources[0x75]	272106	1			T2	768		T4	1173		T8	1
valid_sources[0x76]	372301	1			T2	622		T4	1211		T8	3
valid_sources[0x77]	289086	1			T2	828		T4	1294		T8	3
valid_sources[0x78]	255244	1			T2	755		T4	991		T8	4
valid_sources[0x79]	249070	1			T2	618		T4	1286		T5	32
valid_sources[0x7a]	270946	1			T2	632		T4	1126		T8	4
valid_sources[0x7b]	248536	1			T2	649		T4	1098		T8	6
valid_sources[0x7c]	260553	1			T2	620		T4	1091		T5	41
valid_sources[0x7d]	242636	1			T2	583		T4	1344		T8	3
valid_sources[0x7e]	325655	1			T2	608		T3	5		T4	1376
valid_sources[0x7f]	341793	1			T2	668		T3	1		T4	1308
valid_sources[0x80]	329070	1			T2	538		T4	1341		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29043504

1

T2

74769

T3

43

T4

144552

values[0x0]

all_enables

biggest_size

14617455

1

T2

37126

T3

27

T4

72213

values[0x1]

all_enables

biggest_size

14612802

1

T2

37162

T3

28

T4

72114

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

133985

1

T2

2

T4

24

T5

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49439	1			T4	24		T5	10		T7	34
values[0x0]	58459	1			T2	4		T4	21		T5	3
values[0x1]	62285	1			T1	1		T2	2		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142834

1

T2

2

T4

27

T5

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	574	1			T23	3		T24	4		T109	2
valid_sources[0x01]	1060	1			T23	5		T20	5		T24	4
valid_sources[0x02]	625	1			T7	1		T23	3		T70	1
valid_sources[0x03]	734	1			T23	4		T24	1		T17	16
valid_sources[0x04]	590	1			T7	1		T23	3		T27	1
valid_sources[0x05]	603	1			T7	1		T23	9		T58	1
valid_sources[0x06]	607	1			T23	10		T24	5		T109	2
valid_sources[0x07]	668	1			T23	9		T70	1		T17	36
valid_sources[0x08]	683	1			T23	7		T24	2		T50	3
valid_sources[0x09]	626	1			T23	5		T58	1		T24	4
valid_sources[0x0a]	633	1			T23	6		T26	1		T24	4
valid_sources[0x0b]	564	1			T7	1		T23	5		T69	1
valid_sources[0x0c]	679	1			T5	20		T23	5		T20	3
valid_sources[0x0d]	717	1			T23	3		T53	7		T42	1
valid_sources[0x0e]	756	1			T11	1		T23	8		T24	3
valid_sources[0x0f]	802	1			T23	5		T20	3		T24	5
valid_sources[0x10]	757	1			T23	1		T70	2		T24	12
valid_sources[0x11]	653	1			T23	6		T20	2		T17	20
valid_sources[0x12]	785	1			T2	2		T7	1		T23	1
valid_sources[0x13]	757	1			T23	5		T26	1		T24	1
valid_sources[0x14]	783	1			T23	2		T26	1		T24	7
valid_sources[0x15]	562	1			T7	1		T23	5		T26	1
valid_sources[0x16]	585	1			T23	9		T24	3		T17	1
valid_sources[0x17]	724	1			T7	3		T23	4		T69	1
valid_sources[0x18]	612	1			T23	3		T24	4		T109	1
valid_sources[0x19]	690	1			T7	1		T23	4		T20	1
valid_sources[0x1a]	507	1			T4	9		T23	2		T20	3
valid_sources[0x1b]	706	1			T7	1		T23	5		T24	3
valid_sources[0x1c]	753	1			T23	6		T24	9		T17	19
valid_sources[0x1d]	543	1			T23	12		T69	1		T24	13
valid_sources[0x1e]	694	1			T23	3		T70	1		T24	10
valid_sources[0x1f]	626	1			T7	2		T23	1		T58	1
valid_sources[0x20]	630	1			T7	1		T23	6		T55	5
valid_sources[0x21]	773	1			T23	2		T26	1		T27	1
valid_sources[0x22]	576	1			T23	1		T20	1		T24	2
valid_sources[0x23]	684	1			T7	1		T28	1		T23	2
valid_sources[0x24]	820	1			T23	7		T24	5		T17	2
valid_sources[0x25]	694	1			T23	7		T24	2		T17	27
valid_sources[0x26]	544	1			T23	4		T24	2		T17	18
valid_sources[0x27]	602	1			T7	1		T23	6		T69	1
valid_sources[0x28]	762	1			T4	8		T23	3		T20	2
valid_sources[0x29]	801	1			T23	6		T44	1		T69	1
valid_sources[0x2a]	558	1			T11	1		T23	3		T26	1
valid_sources[0x2b]	632	1			T23	10		T24	4		T50	11
valid_sources[0x2c]	1109	1			T7	2		T23	1		T24	13
valid_sources[0x2d]	785	1			T23	7		T69	1		T24	4
valid_sources[0x2e]	915	1			T23	13		T70	1		T17	25
valid_sources[0x2f]	639	1			T23	5		T53	1		T24	7
valid_sources[0x30]	750	1			T23	4		T24	3		T109	3
valid_sources[0x31]	603	1			T23	4		T69	1		T20	1
valid_sources[0x32]	644	1			T23	7		T27	1		T70	2
valid_sources[0x33]	614	1			T23	2		T27	1		T17	9
valid_sources[0x34]	764	1			T23	3		T42	2		T20	2
valid_sources[0x35]	599	1			T23	4		T24	12		T17	16
valid_sources[0x36]	740	1			T7	2		T23	2		T26	1
valid_sources[0x37]	557	1			T4	5		T23	6		T17	4
valid_sources[0x38]	631	1			T23	2		T24	8		T17	25
valid_sources[0x39]	608	1			T23	4		T24	1		T50	4
valid_sources[0x3a]	816	1			T23	13		T20	2		T24	3
valid_sources[0x3b]	696	1			T7	1		T23	7		T44	1
valid_sources[0x3c]	707	1			T23	3		T24	2		T17	41
valid_sources[0x3d]	572	1			T23	6		T42	3		T70	2
valid_sources[0x3e]	713	1			T23	7		T69	1		T24	2
valid_sources[0x3f]	554	1			T23	5		T20	5		T24	8
valid_sources[0x40]	689	1			T6	4		T7	1		T23	7
valid_sources[0x41]	650	1			T23	5		T69	1		T27	1
valid_sources[0x42]	546	1			T7	1		T23	5		T69	1
valid_sources[0x43]	503	1			T23	7		T20	2		T24	4
valid_sources[0x44]	898	1			T23	11		T69	2		T24	4
valid_sources[0x45]	597	1			T4	5		T7	2		T23	5
valid_sources[0x46]	634	1			T23	4		T24	6		T109	2
valid_sources[0x47]	570	1			T23	3		T12	5		T70	1
valid_sources[0x48]	635	1			T23	5		T53	9		T24	4
valid_sources[0x49]	583	1			T23	3		T24	6		T50	8
valid_sources[0x4a]	652	1			T11	2		T23	4		T24	8
valid_sources[0x4b]	671	1			T23	8		T56	2		T69	1
valid_sources[0x4c]	616	1			T23	2		T20	1		T24	1
valid_sources[0x4d]	603	1			T7	3		T23	4		T27	2
valid_sources[0x4e]	842	1			T23	1		T69	1		T70	1
valid_sources[0x4f]	618	1			T23	6		T20	2		T24	6
valid_sources[0x50]	826	1			T23	5		T70	2		T24	2
valid_sources[0x51]	594	1			T23	5		T26	1		T59	1
valid_sources[0x52]	605	1			T23	11		T69	2		T27	1
valid_sources[0x53]	628	1			T23	3		T20	4		T24	1
valid_sources[0x54]	595	1			T23	4		T26	1		T20	1
valid_sources[0x55]	711	1			T23	1		T24	8		T17	5
valid_sources[0x56]	911	1			T7	1		T23	4		T24	2
valid_sources[0x57]	600	1			T23	10		T69	1		T24	12
valid_sources[0x58]	1022	1			T7	1		T23	4		T27	2
valid_sources[0x59]	1207	1			T23	4		T20	3		T24	4
valid_sources[0x5a]	525	1			T23	2		T24	2		T17	10
valid_sources[0x5b]	723	1			T23	5		T53	7		T69	3
valid_sources[0x5c]	715	1			T23	5		T24	4		T109	1
valid_sources[0x5d]	838	1			T23	1		T24	10		T17	7
valid_sources[0x5e]	535	1			T7	1		T23	3		T69	1
valid_sources[0x5f]	647	1			T23	5		T24	8		T109	1
valid_sources[0x60]	693	1			T23	4		T24	2		T17	20
valid_sources[0x61]	563	1			T23	6		T69	2		T24	6
valid_sources[0x62]	508	1			T23	4		T24	1		T17	1
valid_sources[0x63]	490	1			T23	1		T24	5		T109	1
valid_sources[0x64]	637	1			T23	3		T24	8		T109	1
valid_sources[0x65]	573	1			T8	3		T7	1		T23	5
valid_sources[0x66]	683	1			T7	1		T23	5		T70	2
valid_sources[0x67]	676	1			T7	1		T23	1		T24	4
valid_sources[0x68]	713	1			T23	9		T69	1		T24	5
valid_sources[0x69]	664	1			T7	1		T23	7		T27	2
valid_sources[0x6a]	550	1			T23	4		T20	1		T24	9
valid_sources[0x6b]	878	1			T23	1		T69	1		T70	1
valid_sources[0x6c]	674	1			T23	6		T42	4		T109	1
valid_sources[0x6d]	638	1			T7	2		T23	13		T20	1
valid_sources[0x6e]	569	1			T7	1		T41	1		T23	2
valid_sources[0x6f]	521	1			T4	4		T7	1		T23	9
valid_sources[0x70]	516	1			T23	4		T24	17		T50	3
valid_sources[0x71]	584	1			T23	1		T69	1		T27	1
valid_sources[0x72]	581	1			T23	4		T26	1		T27	1
valid_sources[0x73]	502	1			T7	1		T23	1		T26	1
valid_sources[0x74]	626	1			T4	1		T7	3		T23	5
valid_sources[0x75]	860	1			T23	7		T133	2		T20	3
valid_sources[0x76]	555	1			T7	1		T23	5		T24	5
valid_sources[0x77]	702	1			T23	2		T26	1		T20	1
valid_sources[0x78]	610	1			T23	2		T69	1		T24	5
valid_sources[0x79]	897	1			T11	1		T23	2		T42	8
valid_sources[0x7a]	612	1			T23	1		T20	1		T24	8
valid_sources[0x7b]	534	1			T23	3		T20	2		T24	1
valid_sources[0x7c]	714	1			T10	3		T23	4		T44	2
valid_sources[0x7d]	618	1			T23	8		T20	6		T24	8
valid_sources[0x7e]	579	1			T23	6		T26	1		T70	1
valid_sources[0x7f]	545	1			T23	6		T69	1		T20	3
valid_sources[0x80]	860	1			T25	40		T23	4		T24	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36668

1

T4

13

T5

3

T7

13

values[0x0]

all_enables

biggest_size

50027

1

T2

2

T4

8

T5

1

values[0x1]

all_enables

biggest_size

47290

1

T4

3

T5

1

T7

4