Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14013374

1

T2

14967

T4

28811

T5

22

full_word

53128134

1

T2

149057

T3

98

T4

287448

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67141218	1			T2	164024		T3	98		T4	316259
auto[TlIntgErrCmd]	107	1			T63	3		T64	3		T65	3
auto[TlIntgErrData]	77	1			T63	4		T64	3		T65	3
auto[TlIntgErrBoth]	106	1			T63	3		T64	4		T65	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30673224

1

T2

82353

T3

43

T4

158280

auto[1]

36468284

1

T2

81671

T3

55

T4

157979

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6700062	1			T2	7584		T4	14470		T5	12
auto[TlIntgErrNone]	partial	auto[1]	7313045	1			T2	7383		T4	14341		T5	10
auto[TlIntgErrNone]	full_word	auto[0]	23973044	1			T2	74769		T3	43		T4	143810
auto[TlIntgErrNone]	full_word	auto[1]	29155067	1			T2	74288		T3	55		T4	143638
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T63	1		T64	1		T65	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T63	1		T64	2		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T113	1		T121	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T63	1		T113	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T63	3		T65	1		T115	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T63	1		T64	3		T65	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T122	1		T123	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1			T116	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T63	2		T65	2		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T63	1		T64	3		T65	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T64	1		T113	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T65	1		T113	1		T124	1