Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	665779	1			T7	12		T10	256		T25	23
auto[1]	10851844	1			T2	69163		T3	43		T4	67311
auto[2]	546256	1			T7	9		T10	171		T25	24
auto[3]	10739037	1			T2	68566		T3	54		T4	66895

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14185877	1			T2	113873		T3	97		T4	112107
auto[1]	2224534	1			T2	11294		T4	10410		T5	16
auto[2]	2232893	1			T2	11429		T4	10685		T5	14
auto[3]	4159612	1			T2	1133		T4	1004		T5	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8677551

1

T3

97

T4

134077

T5

252

auto[1]

14125365

1

T2

137729

T4

129

T8

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	230452	1			T7	11		T25	18		T23	718
auto[0]	auto[0]	auto[1]	23489	1			T10	3		T25	2		T22	1
auto[0]	auto[0]	auto[2]	23345	1			T7	1		T10	5		T25	3
auto[0]	auto[0]	auto[3]	6611	1			T10	248		T22	3		T23	6
auto[0]	auto[1]	auto[0]	3340322	1			T3	43		T4	56220		T5	103
auto[0]	auto[1]	auto[1]	341275	1			T4	4925		T5	7		T8	3
auto[0]	auto[1]	auto[2]	337704	1			T4	5604		T5	8		T8	33
auto[0]	auto[1]	auto[3]	75609	1			T4	509		T5	1		T8	321
auto[0]	auto[2]	auto[0]	194555	1			T7	6		T23	625		T69	14
auto[0]	auto[2]	auto[1]	19827	1			T7	1		T10	14		T22	2
auto[0]	auto[2]	auto[2]	21609	1			T7	2		T25	22		T23	52
auto[0]	auto[2]	auto[3]	5313	1			T10	157		T25	2		T22	4
auto[0]	auto[3]	auto[0]	3304132	1			T3	54		T4	55773		T5	118
auto[0]	auto[3]	auto[1]	335148	1			T4	5477		T5	9		T8	56
auto[0]	auto[3]	auto[2]	340648	1			T4	5075		T5	6		T8	50
auto[0]	auto[3]	auto[3]	77512	1			T4	494		T8	454		T10	262
auto[1]	auto[0]	auto[0]	12712	1			T22	596		T23	1		T69	1
auto[1]	auto[0]	auto[1]	56501	1			T22	2640		T125	7		T130	422
auto[1]	auto[0]	auto[2]	56744	1			T22	2664		T69	1		T125	1
auto[1]	auto[0]	auto[3]	255925	1			T22	12166		T128	2		T129	2
auto[1]	auto[1]	auto[0]	3548676	1			T2	57159		T4	47		T6	3361
auto[1]	auto[1]	auto[1]	716369	1			T2	5678		T4	5		T6	13156
auto[1]	auto[1]	auto[2]	701369	1			T2	5760		T4	1		T6	14754
auto[1]	auto[1]	auto[3]	1790520	1			T2	566		T8	1		T6	59836
auto[1]	auto[2]	auto[0]	9914	1			T22	545		T125	8		T19	1
auto[1]	auto[2]	auto[1]	43697	1			T22	2498		T125	2		T19	1
auto[1]	auto[2]	auto[2]	45513	1			T22	2240		T20	1		T127	1
auto[1]	auto[2]	auto[3]	205828	1			T22	10117		T130	1684		T131	2285
auto[1]	auto[3]	auto[0]	3545114	1			T2	56714		T4	67		T6	3372
auto[1]	auto[3]	auto[1]	688228	1			T2	5616		T4	3		T6	14705
auto[1]	auto[3]	auto[2]	705961	1			T2	5669		T4	5		T6	13344
auto[1]	auto[3]	auto[3]	1742294	1			T2	567		T4	1		T8	1