Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	296868413	195824	0	0
ctrl_regwen_rd_A	296868413	4299	0	0
exec_rd_A	296868413	3963	0	0
exec_regwen_rd_A	296868413	4300	0	0
readback_rd_A	296868413	2564	0	0
readback_regwen_rd_A	296868413	2048	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296868413	195824	0	0
T17	0	5872	0	0
T23	115576	1415	0	0
T24	0	2132	0	0
T26	287898	0	0	0
T44	17758	0	0	0
T45	0	1138	0	0
T50	0	2844	0	0
T51	0	11000	0	0
T52	0	5522	0	0
T53	62718	0	0	0
T54	8847	0	0	0
T55	6571	0	0	0
T56	6967	0	0	0
T57	4002	0	0	0
T58	286580	0	0	0
T59	199658	0	0	0
T60	0	7402	0	0
T62	0	6605	0	0
T71	0	3431	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296868413	4299	0	0
T13	938	0	0	0
T17	92991	0	0	0
T24	123057	61	0	0
T43	232186	0	0	0
T45	0	66	0	0
T52	0	220	0	0
T72	11224	0	0	0
T87	6677	0	0	0
T99	382480	0	0	0
T102	0	120	0	0
T103	0	301	0	0
T104	0	404	0	0
T105	0	563	0	0
T106	0	163	0	0
T107	0	61	0	0
T108	0	328	0	0
T109	521469	0	0	0
T110	9177	0	0	0
T111	836	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296868413	3963	0	0
T13	938	0	0	0
T17	92991	0	0	0
T24	123057	58	0	0
T43	232186	0	0	0
T45	0	71	0	0
T52	0	207	0	0
T72	11224	0	0	0
T87	6677	0	0	0
T99	382480	0	0	0
T102	0	86	0	0
T103	0	221	0	0
T104	0	387	0	0
T105	0	413	0	0
T106	0	191	0	0
T107	0	105	0	0
T108	0	339	0	0
T109	521469	0	0	0
T110	9177	0	0	0
T111	836	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296868413	4300	0	0
T13	938	0	0	0
T17	92991	0	0	0
T24	123057	89	0	0
T43	232186	0	0	0
T45	0	38	0	0
T52	0	213	0	0
T72	11224	0	0	0
T87	6677	0	0	0
T99	382480	0	0	0
T102	0	145	0	0
T103	0	232	0	0
T104	0	378	0	0
T105	0	513	0	0
T106	0	178	0	0
T107	0	69	0	0
T108	0	364	0	0
T109	521469	0	0	0
T110	9177	0	0	0
T111	836	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296868413	2564	0	0
T13	938	0	0	0
T17	92991	0	0	0
T24	123057	50	0	0
T43	232186	0	0	0
T45	0	45	0	0
T52	0	190	0	0
T72	11224	0	0	0
T87	6677	0	0	0
T99	382480	0	0	0
T102	0	86	0	0
T103	0	159	0	0
T104	0	411	0	0
T105	0	432	0	0
T106	0	166	0	0
T107	0	63	0	0
T108	0	266	0	0
T109	521469	0	0	0
T110	9177	0	0	0
T111	836	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296868413	2048	0	0
T13	938	0	0	0
T17	92991	0	0	0
T24	123057	35	0	0
T43	232186	0	0	0
T45	0	23	0	0
T52	0	186	0	0
T72	11224	0	0	0
T87	6677	0	0	0
T99	382480	0	0	0
T102	0	50	0	0
T103	0	189	0	0
T104	0	353	0	0
T105	0	376	0	0
T106	0	139	0	0
T107	0	11	0	0
T108	0	255	0	0
T109	521469	0	0	0
T110	9177	0	0	0
T111	836	0	0	0