Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14454140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58363511

1

T1

114287

T3

5177

T4

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36299446	1			T1	62815		T3	2613		T4	350
values[0x0]	16811453	1			T1	30178		T3	1259		T4	196
values[0x1]	19706752	1			T1	32675		T3	1305		T4	407

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7201521	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65616130

1

T1

120024

T3

5177

T4

422

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	246288	1			T1	529		T4	4		T5	11
valid_sources[0x01]	290250	1			T1	502		T4	12		T5	17
valid_sources[0x02]	284081	1			T1	494		T5	11		T10	225
valid_sources[0x03]	280065	1			T1	483		T4	7		T5	5
valid_sources[0x04]	303173	1			T1	508		T4	1		T5	6
valid_sources[0x05]	256990	1			T1	524		T4	3		T5	11
valid_sources[0x06]	318676	1			T1	500		T4	9		T5	12
valid_sources[0x07]	278789	1			T1	446		T5	13		T10	134
valid_sources[0x08]	281824	1			T1	424		T5	8		T10	136
valid_sources[0x09]	244549	1			T1	463		T4	3		T5	9
valid_sources[0x0a]	280497	1			T1	527		T4	7		T5	10
valid_sources[0x0b]	276010	1			T1	437		T4	4		T5	12
valid_sources[0x0c]	258951	1			T1	528		T4	3		T5	9
valid_sources[0x0d]	303215	1			T1	514		T4	10		T5	11
valid_sources[0x0e]	310150	1			T1	463		T5	8		T10	119
valid_sources[0x0f]	274246	1			T1	502		T4	2		T5	12
valid_sources[0x10]	253954	1			T1	518		T4	14		T5	14
valid_sources[0x11]	278981	1			T1	495		T4	1		T5	7
valid_sources[0x12]	270725	1			T1	564		T4	2		T5	17
valid_sources[0x13]	296510	1			T1	513		T4	3		T5	9
valid_sources[0x14]	281211	1			T1	487		T4	6		T5	17
valid_sources[0x15]	254476	1			T1	574		T4	5		T5	7
valid_sources[0x16]	290080	1			T1	529		T4	1		T5	8
valid_sources[0x17]	254039	1			T1	517		T4	7		T5	13
valid_sources[0x18]	267811	1			T1	467		T4	2		T5	9
valid_sources[0x19]	267668	1			T1	410		T4	1		T5	13
valid_sources[0x1a]	252264	1			T1	492		T4	7		T5	10
valid_sources[0x1b]	291893	1			T1	504		T4	5		T5	9
valid_sources[0x1c]	282735	1			T1	536		T5	10		T10	186
valid_sources[0x1d]	279912	1			T1	452		T4	3		T5	20
valid_sources[0x1e]	274422	1			T1	482		T5	13		T10	109
valid_sources[0x1f]	310374	1			T1	483		T4	13		T5	16
valid_sources[0x20]	285926	1			T1	489		T4	2		T5	12
valid_sources[0x21]	283815	1			T1	503		T4	4		T5	12
valid_sources[0x22]	248467	1			T1	458		T4	2		T5	14
valid_sources[0x23]	274447	1			T1	468		T5	16		T10	171
valid_sources[0x24]	276685	1			T1	518		T4	6		T5	16
valid_sources[0x25]	292217	1			T1	495		T4	2		T5	4
valid_sources[0x26]	243469	1			T1	483		T4	5		T5	15
valid_sources[0x27]	259236	1			T1	485		T4	2		T5	5
valid_sources[0x28]	289643	1			T1	540		T4	6		T5	14
valid_sources[0x29]	311566	1			T1	559		T4	5		T5	12
valid_sources[0x2a]	259598	1			T1	435		T4	4		T5	15
valid_sources[0x2b]	280065	1			T1	544		T4	5		T5	6
valid_sources[0x2c]	290027	1			T1	555		T5	10		T10	139
valid_sources[0x2d]	284248	1			T1	487		T4	1		T5	8
valid_sources[0x2e]	274815	1			T1	533		T4	6		T5	16
valid_sources[0x2f]	275175	1			T1	486		T4	6		T5	7
valid_sources[0x30]	259102	1			T1	534		T4	15		T5	8
valid_sources[0x31]	261663	1			T1	472		T4	5		T5	10
valid_sources[0x32]	285418	1			T1	491		T4	5		T5	22
valid_sources[0x33]	297469	1			T1	467		T4	3		T5	12
valid_sources[0x34]	330302	1			T1	493		T5	8		T10	223
valid_sources[0x35]	247628	1			T1	471		T5	13		T10	147
valid_sources[0x36]	280804	1			T1	515		T4	2		T5	17
valid_sources[0x37]	283374	1			T1	495		T4	5		T5	6
valid_sources[0x38]	295132	1			T1	559		T4	10		T5	10
valid_sources[0x39]	255110	1			T1	543		T4	8		T5	15
valid_sources[0x3a]	256511	1			T1	520		T4	3		T5	7
valid_sources[0x3b]	330002	1			T1	536		T4	4		T5	7
valid_sources[0x3c]	268729	1			T1	433		T4	3		T5	19
valid_sources[0x3d]	281434	1			T1	496		T5	14		T10	141
valid_sources[0x3e]	281431	1			T1	553		T4	1		T5	20
valid_sources[0x3f]	246252	1			T1	492		T4	4		T5	12
valid_sources[0x40]	257781	1			T1	504		T4	1		T5	11
valid_sources[0x41]	273507	1			T1	506		T4	1		T5	22
valid_sources[0x42]	250949	1			T1	487		T5	14		T10	153
valid_sources[0x43]	286616	1			T1	495		T4	2		T5	14
valid_sources[0x44]	268518	1			T1	459		T4	1		T5	12
valid_sources[0x45]	336335	1			T1	488		T5	14		T10	163
valid_sources[0x46]	270062	1			T1	519		T4	2		T5	12
valid_sources[0x47]	261082	1			T1	500		T5	14		T10	108
valid_sources[0x48]	319995	1			T1	464		T5	11		T10	222
valid_sources[0x49]	248753	1			T1	480		T4	2		T5	10
valid_sources[0x4a]	357935	1			T1	481		T4	1		T5	13
valid_sources[0x4b]	270542	1			T1	442		T4	4		T5	14
valid_sources[0x4c]	324750	1			T1	477		T4	8		T5	16
valid_sources[0x4d]	281561	1			T1	480		T3	2589		T4	1
valid_sources[0x4e]	263415	1			T1	485		T4	7		T5	14
valid_sources[0x4f]	269150	1			T1	504		T4	4		T5	11
valid_sources[0x50]	344814	1			T1	457		T4	10		T5	16
valid_sources[0x51]	278601	1			T1	475		T4	7		T5	11
valid_sources[0x52]	281048	1			T1	478		T4	2		T5	13
valid_sources[0x53]	302448	1			T1	471		T4	1		T5	5
valid_sources[0x54]	255219	1			T1	501		T4	4		T5	21
valid_sources[0x55]	274754	1			T1	468		T5	11		T10	218
valid_sources[0x56]	256976	1			T1	530		T4	5		T5	13
valid_sources[0x57]	262178	1			T1	450		T4	4		T5	17
valid_sources[0x58]	268140	1			T1	510		T3	2588		T5	17
valid_sources[0x59]	258410	1			T1	540		T4	1		T5	8
valid_sources[0x5a]	287170	1			T1	520		T4	1		T5	20
valid_sources[0x5b]	283747	1			T1	498		T4	13		T5	10
valid_sources[0x5c]	351659	1			T1	514		T5	17		T10	86
valid_sources[0x5d]	299218	1			T1	488		T5	16		T10	210
valid_sources[0x5e]	293819	1			T1	435		T4	10		T5	7
valid_sources[0x5f]	282350	1			T1	462		T4	1		T5	12
valid_sources[0x60]	271702	1			T1	511		T4	3		T5	11
valid_sources[0x61]	251952	1			T1	475		T4	1		T5	10
valid_sources[0x62]	321856	1			T1	474		T4	7		T5	11
valid_sources[0x63]	289341	1			T1	532		T4	10		T5	10
valid_sources[0x64]	293712	1			T1	521		T4	4		T5	14
valid_sources[0x65]	300835	1			T1	462		T5	8		T10	106
valid_sources[0x66]	331761	1			T1	515		T4	1		T5	16
valid_sources[0x67]	272698	1			T1	537		T4	8		T5	5
valid_sources[0x68]	294171	1			T1	464		T4	2		T5	17
valid_sources[0x69]	282108	1			T1	471		T4	1		T5	15
valid_sources[0x6a]	289368	1			T1	447		T4	2		T5	14
valid_sources[0x6b]	255311	1			T1	446		T4	4		T5	12
valid_sources[0x6c]	253971	1			T1	451		T5	9		T10	154
valid_sources[0x6d]	316953	1			T1	575		T5	11		T10	143
valid_sources[0x6e]	243437	1			T1	483		T4	1		T5	5
valid_sources[0x6f]	256179	1			T1	435		T4	7		T5	11
valid_sources[0x70]	265024	1			T1	560		T4	10		T5	10
valid_sources[0x71]	275123	1			T1	465		T4	1		T5	7
valid_sources[0x72]	309231	1			T1	556		T4	1		T5	8
valid_sources[0x73]	330779	1			T1	461		T4	4		T5	19
valid_sources[0x74]	260211	1			T1	577		T4	9		T5	8
valid_sources[0x75]	254255	1			T1	454		T4	3		T5	13
valid_sources[0x76]	246797	1			T1	513		T5	12		T10	184
valid_sources[0x77]	287556	1			T1	470		T4	2		T5	19
valid_sources[0x78]	253727	1			T1	500		T4	1		T5	12
valid_sources[0x79]	269758	1			T1	461		T4	1		T5	12
valid_sources[0x7a]	300011	1			T1	474		T4	1		T5	7
valid_sources[0x7b]	324063	1			T1	466		T5	12		T10	146
valid_sources[0x7c]	297650	1			T1	504		T4	4		T5	10
valid_sources[0x7d]	269928	1			T1	546		T4	5		T5	18
valid_sources[0x7e]	261244	1			T1	418		T4	4		T5	13
valid_sources[0x7f]	331172	1			T1	474		T4	12		T5	14
valid_sources[0x80]	280825	1			T1	474		T4	2		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29081266

1

T1

57080

T3

2613

T4

2

values[0x0]

all_enables

biggest_size

14641642

1

T1

28461

T3

1259

T4

22

values[0x1]

all_enables

biggest_size

14640603

1

T1

28746

T3

1305

T4

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141025

1

T2

2

T4

2

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51837	1			T7	16		T27	8		T20	17
values[0x0]	60816	1			T1	3		T2	3		T3	2
values[0x1]	65846	1			T1	3		T2	5		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150151

1

T1

1

T2

3

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1077	1			T12	2		T13	2		T28	6
valid_sources[0x01]	631	1			T14	16		T30	6		T60	4
valid_sources[0x02]	539	1			T83	1		T60	4		T57	7
valid_sources[0x03]	693	1			T28	21		T9	2		T21	1
valid_sources[0x04]	719	1			T28	19		T24	89		T29	1
valid_sources[0x05]	542	1			T60	1		T57	20		T23	1
valid_sources[0x06]	675	1			T31	2		T9	1		T139	1
valid_sources[0x07]	575	1			T28	27		T22	1		T21	2
valid_sources[0x08]	848	1			T28	10		T29	4		T30	5
valid_sources[0x09]	911	1			T28	18		T22	1		T29	154
valid_sources[0x0a]	461	1			T28	17		T9	1		T22	1
valid_sources[0x0b]	418	1			T28	2		T21	1		T29	1
valid_sources[0x0c]	753	1			T28	1		T9	1		T22	1
valid_sources[0x0d]	680	1			T28	1		T22	1		T21	1
valid_sources[0x0e]	875	1			T28	4		T83	2		T60	3
valid_sources[0x0f]	581	1			T137	1		T140	2		T30	5
valid_sources[0x10]	645	1			T28	4		T22	2		T29	1
valid_sources[0x11]	897	1			T9	1		T21	1		T60	2
valid_sources[0x12]	648	1			T141	1		T30	7		T122	1
valid_sources[0x13]	683	1			T28	1		T9	1		T21	1
valid_sources[0x14]	857	1			T28	1		T137	1		T30	26
valid_sources[0x15]	631	1			T28	7		T29	73		T142	2
valid_sources[0x16]	525	1			T31	1		T28	2		T81	1
valid_sources[0x17]	723	1			T48	1		T8	2		T28	8
valid_sources[0x18]	785	1			T48	1		T28	1		T9	1
valid_sources[0x19]	611	1			T28	4		T9	1		T22	1
valid_sources[0x1a]	862	1			T1	1		T28	2		T22	1
valid_sources[0x1b]	752	1			T28	3		T22	1		T83	1
valid_sources[0x1c]	812	1			T28	5		T83	2		T30	18
valid_sources[0x1d]	490	1			T28	1		T21	2		T29	1
valid_sources[0x1e]	585	1			T48	2		T28	11		T83	1
valid_sources[0x1f]	721	1			T28	14		T22	1		T81	1
valid_sources[0x20]	530	1			T22	2		T29	3		T30	5
valid_sources[0x21]	543	1			T9	1		T140	2		T30	5
valid_sources[0x22]	431	1			T48	2		T22	2		T83	1
valid_sources[0x23]	785	1			T11	2		T8	1		T22	1
valid_sources[0x24]	776	1			T31	2		T8	1		T29	2
valid_sources[0x25]	760	1			T81	1		T83	1		T140	2
valid_sources[0x26]	707	1			T12	4		T28	23		T22	4
valid_sources[0x27]	547	1			T48	1		T28	2		T83	2
valid_sources[0x28]	559	1			T31	1		T9	1		T22	1
valid_sources[0x29]	704	1			T28	4		T29	1		T30	1
valid_sources[0x2a]	687	1			T70	1		T28	6		T79	1
valid_sources[0x2b]	502	1			T31	1		T48	1		T9	1
valid_sources[0x2c]	702	1			T28	7		T21	1		T57	7
valid_sources[0x2d]	643	1			T28	5		T9	1		T140	1
valid_sources[0x2e]	621	1			T106	6		T79	1		T141	1
valid_sources[0x2f]	771	1			T48	3		T28	5		T9	2
valid_sources[0x30]	698	1			T8	3		T28	11		T29	1
valid_sources[0x31]	659	1			T77	6		T22	1		T29	94
valid_sources[0x32]	738	1			T28	2		T22	2		T29	7
valid_sources[0x33]	769	1			T28	1		T22	1		T29	47
valid_sources[0x34]	701	1			T9	1		T29	1		T30	42
valid_sources[0x35]	599	1			T16	1		T28	3		T29	2
valid_sources[0x36]	790	1			T28	21		T29	3		T60	4
valid_sources[0x37]	616	1			T28	1		T83	3		T140	1
valid_sources[0x38]	492	1			T48	1		T28	2		T29	3
valid_sources[0x39]	620	1			T28	13		T141	1		T29	1
valid_sources[0x3a]	795	1			T27	37		T28	8		T22	1
valid_sources[0x3b]	771	1			T1	1		T9	1		T22	2
valid_sources[0x3c]	446	1			T69	1		T22	2		T29	3
valid_sources[0x3d]	579	1			T28	1		T80	6		T29	1
valid_sources[0x3e]	549	1			T4	1		T48	1		T139	1
valid_sources[0x3f]	722	1			T8	3		T28	1		T9	2
valid_sources[0x40]	468	1			T28	15		T141	1		T29	5
valid_sources[0x41]	672	1			T28	25		T29	2		T30	7
valid_sources[0x42]	790	1			T28	6		T22	1		T60	4
valid_sources[0x43]	549	1			T22	1		T141	2		T29	1
valid_sources[0x44]	903	1			T28	5		T29	11		T60	4
valid_sources[0x45]	683	1			T31	1		T28	1		T9	1
valid_sources[0x46]	1102	1			T83	3		T140	1		T30	78
valid_sources[0x47]	1138	1			T22	2		T30	1		T60	3
valid_sources[0x48]	881	1			T22	1		T30	4		T60	11
valid_sources[0x49]	906	1			T140	1		T60	4		T57	12
valid_sources[0x4a]	575	1			T2	2		T22	1		T60	8
valid_sources[0x4b]	699	1			T9	1		T29	2		T122	5
valid_sources[0x4c]	552	1			T30	1		T60	4		T57	21
valid_sources[0x4d]	731	1			T28	3		T22	2		T107	1
valid_sources[0x4e]	1088	1			T9	1		T30	11		T60	5
valid_sources[0x4f]	560	1			T28	1		T30	4		T57	19
valid_sources[0x50]	538	1			T71	1		T92	3		T28	22
valid_sources[0x51]	597	1			T28	4		T83	1		T60	2
valid_sources[0x52]	537	1			T28	4		T9	1		T140	1
valid_sources[0x53]	782	1			T28	15		T141	1		T29	2
valid_sources[0x54]	528	1			T12	7		T143	1		T28	14
valid_sources[0x55]	798	1			T28	12		T9	1		T30	2
valid_sources[0x56]	755	1			T28	8		T9	1		T29	1
valid_sources[0x57]	840	1			T28	10		T22	2		T29	1
valid_sources[0x58]	499	1			T28	5		T21	2		T83	1
valid_sources[0x59]	673	1			T31	1		T140	1		T30	1
valid_sources[0x5a]	923	1			T65	1		T28	5		T9	1
valid_sources[0x5b]	1065	1			T28	1		T81	1		T141	2
valid_sources[0x5c]	952	1			T28	2		T29	89		T60	7
valid_sources[0x5d]	613	1			T48	1		T95	1		T60	3
valid_sources[0x5e]	763	1			T22	1		T29	155		T83	1
valid_sources[0x5f]	598	1			T2	1		T83	1		T140	1
valid_sources[0x60]	536	1			T28	1		T22	1		T21	1
valid_sources[0x61]	612	1			T31	2		T28	7		T22	1
valid_sources[0x62]	899	1			T28	8		T141	1		T29	69
valid_sources[0x63]	859	1			T9	1		T22	1		T21	1
valid_sources[0x64]	576	1			T28	1		T22	2		T144	18
valid_sources[0x65]	593	1			T28	29		T29	10		T60	3
valid_sources[0x66]	765	1			T10	20		T49	1		T28	5
valid_sources[0x67]	647	1			T31	1		T9	1		T83	1
valid_sources[0x68]	500	1			T12	3		T49	1		T83	2
valid_sources[0x69]	1227	1			T28	5		T29	1		T83	2
valid_sources[0x6a]	693	1			T49	1		T29	3		T83	2
valid_sources[0x6b]	654	1			T22	1		T141	1		T29	3
valid_sources[0x6c]	865	1			T12	3		T8	2		T28	4
valid_sources[0x6d]	490	1			T12	2		T22	1		T29	1
valid_sources[0x6e]	835	1			T31	1		T16	1		T9	1
valid_sources[0x6f]	472	1			T28	1		T30	8		T122	3
valid_sources[0x70]	1090	1			T65	1		T22	3		T30	14
valid_sources[0x71]	727	1			T29	1		T83	1		T140	1
valid_sources[0x72]	746	1			T28	3		T83	2		T140	1
valid_sources[0x73]	688	1			T28	1		T29	1		T83	1
valid_sources[0x74]	734	1			T28	1		T81	1		T29	154
valid_sources[0x75]	791	1			T20	133		T28	12		T22	1
valid_sources[0x76]	792	1			T29	74		T140	2		T60	4
valid_sources[0x77]	513	1			T22	1		T83	3		T140	1
valid_sources[0x78]	634	1			T9	1		T60	3		T57	6
valid_sources[0x79]	486	1			T4	1		T8	1		T28	29
valid_sources[0x7a]	790	1			T28	17		T60	3		T57	7
valid_sources[0x7b]	601	1			T31	2		T48	3		T28	16
valid_sources[0x7c]	856	1			T22	2		T30	5		T60	10
valid_sources[0x7d]	706	1			T28	2		T137	1		T83	1
valid_sources[0x7e]	508	1			T28	12		T9	1		T60	4
valid_sources[0x7f]	797	1			T8	3		T28	6		T9	1
valid_sources[0x80]	829	1			T22	1		T29	28		T83	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38694

1

T7

10

T27

2

T20

9

values[0x0]

all_enables

biggest_size

52098

1

T2

2

T4

2

T5

1

values[0x1]

all_enables

biggest_size

50233

1

T10

2

T11

2

T12

4