Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14173070

1

T1

11381

T4

902

T6

78040

full_word

53457394

1

T1

114287

T3

5177

T4

51

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67630144	1			T1	125668		T3	5177		T4	953
auto[TlIntgErrCmd]	113	1			T61	7		T62	4		T63	7
auto[TlIntgErrData]	106	1			T61	5		T62	9		T63	6
auto[TlIntgErrBoth]	101	1			T61	8		T62	7		T63	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31030887

1

T1

62815

T3

2613

T4

350

auto[1]

36599577

1

T1

62853

T3

2564

T4

603

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6778438	1			T1	5735		T4	348		T6	39055
auto[TlIntgErrNone]	partial	auto[1]	7394336	1			T1	5646		T4	554		T6	38985
auto[TlIntgErrNone]	full_word	auto[0]	24252295	1			T1	57080		T3	2613		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	29205075	1			T1	57207		T3	2564		T4	49
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T61	1		T62	4		T63	4
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T61	6		T63	3		T123	7
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T124	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T61	1		T62	6		T63	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T61	4		T62	3		T63	4
auto[TlIntgErrData]	full_word	auto[0]	11	1			T63	1		T123	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T123	1		T126	1		T127	2
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T61	3		T62	5		T63	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T61	3		T62	2		T63	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T61	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T61	1		T128	1		T127	1