Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	802113	1			T26	15		T46	21		T47	3184
auto[1]	10225791	1			T1	52771		T3	2608		T6	36997
auto[2]	662953	1			T26	26		T46	16		T47	2317
auto[3]	10093042	1			T1	52815		T3	2563		T6	36832

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13709108	1			T1	87514		T3	5171		T6	2701
auto[1]	2103306	1			T1	8482		T6	11225		T12	5277
auto[2]	2117278	1			T1	8703		T6	11266		T12	5213
auto[3]	3854207	1			T1	887		T6	48637		T12	558

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7951362

1

T3

5170

T6

22

T12

63675

auto[1]

13832537

1

T1

105586

T3

1

T6

73807

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	251153	1			T26	12		T46	17		T7	6
auto[0]	auto[0]	auto[1]	26272	1			T26	1		T46	2		T20	636
auto[0]	auto[0]	auto[2]	26184	1			T26	2		T46	2		T7	1
auto[0]	auto[0]	auto[3]	8572	1			T20	67		T71	109		T9	124
auto[0]	auto[1]	auto[0]	3018388	1			T3	2607		T12	26155		T13	3033
auto[0]	auto[1]	auto[1]	314965	1			T6	1		T12	2666		T26	81
auto[0]	auto[1]	auto[2]	305324	1			T6	2		T12	2609		T26	33
auto[0]	auto[1]	auto[3]	72200	1			T6	3		T12	271		T26	6
auto[0]	auto[2]	auto[0]	207554	1			T7	2		T20	5529		T9	10860
auto[0]	auto[2]	auto[1]	21647	1			T20	541		T9	1043		T22	49
auto[0]	auto[2]	auto[2]	26119	1			T26	24		T46	14		T7	2
auto[0]	auto[2]	auto[3]	7304	1			T26	2		T46	2		T20	53
auto[0]	auto[3]	auto[0]	2975423	1			T3	2563		T12	26484		T13	2932
auto[0]	auto[3]	auto[1]	300623	1			T6	3		T12	2606		T26	35
auto[0]	auto[3]	auto[2]	315959	1			T6	4		T12	2597		T26	100
auto[0]	auto[3]	auto[3]	73675	1			T6	9		T12	287		T26	6
auto[1]	auto[0]	auto[0]	16591	1			T47	94		T20	5		T9	10
auto[1]	auto[0]	auto[1]	72856	1			T47	480		T79	896		T80	4263
auto[1]	auto[0]	auto[2]	73259	1			T47	429		T9	1		T79	870
auto[1]	auto[0]	auto[3]	327226	1			T47	2181		T9	1		T79	4151
auto[1]	auto[1]	auto[0]	3616665	1			T1	43740		T3	1		T6	1345
auto[1]	auto[1]	auto[1]	682017	1			T1	4203		T6	5320		T12	2
auto[1]	auto[1]	auto[2]	641475	1			T1	4385		T6	5879		T12	5
auto[1]	auto[1]	auto[3]	1574757	1			T1	443		T6	24447		T47	7366
auto[1]	auto[2]	auto[0]	12795	1			T20	2		T9	9		T80	854
auto[1]	auto[2]	auto[1]	56996	1			T9	2		T80	3862		T118	951
auto[1]	auto[2]	auto[2]	60332	1			T47	432		T20	2		T79	849
auto[1]	auto[2]	auto[3]	270206	1			T47	1885		T79	3769		T80	16056
auto[1]	auto[3]	auto[0]	3610539	1			T1	43774		T6	1356		T12	18
auto[1]	auto[3]	auto[1]	627930	1			T1	4279		T6	5901		T12	3
auto[1]	auto[3]	auto[2]	668626	1			T1	4318		T6	5381		T12	2
auto[1]	auto[3]	auto[3]	1520267	1			T1	444		T6	24178		T47	7176