Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328863163	215208	0	0
ctrl_regwen_rd_A	328863163	4985	0	0
exec_rd_A	328863163	4865	0	0
exec_regwen_rd_A	328863163	4891	0	0
readback_rd_A	328863163	2494	0	0
readback_regwen_rd_A	328863163	2211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328863163	215208	0	0
T9	350972	0	0	0
T22	175193	0	0	0
T28	26549	1269	0	0
T29	0	6484	0	0
T30	0	1988	0	0
T50	0	2327	0	0
T51	0	1294	0	0
T57	0	6336	0	0
T60	0	1037	0	0
T72	0	6906	0	0
T73	0	3412	0	0
T74	0	3895	0	0
T75	304735	0	0	0
T76	14895	0	0	0
T77	186345	0	0	0
T78	282139	0	0	0
T79	190859	0	0	0
T80	171239	0	0	0
T81	103266	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328863163	4985	0	0
T51	0	62	0	0
T52	0	132	0	0
T53	0	118	0	0
T54	9346	0	0	0
T57	126171	0	0	0
T58	44101	0	0	0
T60	19070	44	0	0
T110	0	139	0	0
T111	0	76	0	0
T112	0	147	0	0
T113	0	109	0	0
T114	0	545	0	0
T115	0	259	0	0
T116	204394	0	0	0
T117	156804	0	0	0
T118	120934	0	0	0
T119	10001	0	0	0
T120	72894	0	0	0
T121	223380	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328863163	4865	0	0
T51	0	70	0	0
T52	0	116	0	0
T53	0	85	0	0
T54	9346	0	0	0
T57	126171	0	0	0
T58	44101	0	0	0
T60	19070	29	0	0
T110	0	132	0	0
T111	0	107	0	0
T112	0	161	0	0
T113	0	106	0	0
T114	0	478	0	0
T115	0	212	0	0
T116	204394	0	0	0
T117	156804	0	0	0
T118	120934	0	0	0
T119	10001	0	0	0
T120	72894	0	0	0
T121	223380	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328863163	4891	0	0
T51	0	91	0	0
T52	0	104	0	0
T53	0	111	0	0
T54	9346	0	0	0
T57	126171	0	0	0
T58	44101	0	0	0
T60	19070	43	0	0
T110	0	103	0	0
T111	0	61	0	0
T112	0	152	0	0
T113	0	101	0	0
T114	0	511	0	0
T115	0	260	0	0
T116	204394	0	0	0
T117	156804	0	0	0
T118	120934	0	0	0
T119	10001	0	0	0
T120	72894	0	0	0
T121	223380	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328863163	2494	0	0
T51	0	80	0	0
T52	0	150	0	0
T53	0	73	0	0
T54	9346	0	0	0
T57	126171	0	0	0
T58	44101	0	0	0
T60	19070	65	0	0
T110	0	128	0	0
T111	0	117	0	0
T112	0	94	0	0
T113	0	100	0	0
T114	0	504	0	0
T115	0	229	0	0
T116	204394	0	0	0
T117	156804	0	0	0
T118	120934	0	0	0
T119	10001	0	0	0
T120	72894	0	0	0
T121	223380	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328863163	2211	0	0
T51	0	101	0	0
T52	0	92	0	0
T53	0	87	0	0
T54	9346	0	0	0
T57	126171	0	0	0
T58	44101	0	0	0
T60	19070	34	0	0
T110	0	94	0	0
T111	0	78	0	0
T112	0	123	0	0
T113	0	92	0	0
T114	0	418	0	0
T115	0	227	0	0
T116	204394	0	0	0
T117	156804	0	0	0
T118	120934	0	0	0
T119	10001	0	0	0
T120	72894	0	0	0
T121	223380	0	0	0