Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14980316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61330628

1

T1

56328

T2

22528

T3

51200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38040741	1			T1	155311		T2	11264		T3	25600
values[0x0]	17637436	1			T1	51808		T2	5662		T3	12797
values[0x1]	20632767	1			T1	103628		T2	5602		T3	12803

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7461344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68849600

1

T1

184658

T2

22528

T3

51200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	287058	1			T1	1003		T2	87		T3	185
valid_sources[0x01]	328043	1			T1	1121		T2	98		T3	177
valid_sources[0x02]	293309	1			T1	1050		T2	86		T3	194
valid_sources[0x03]	375079	1			T1	1186		T2	67		T3	194
valid_sources[0x04]	295756	1			T1	1135		T2	83		T3	199
valid_sources[0x05]	336108	1			T1	1105		T2	74		T3	185
valid_sources[0x06]	331800	1			T1	1213		T2	86		T3	177
valid_sources[0x07]	274768	1			T1	1229		T2	67		T3	214
valid_sources[0x08]	284179	1			T1	1332		T2	108		T3	188
valid_sources[0x09]	274184	1			T1	1354		T2	73		T3	190
valid_sources[0x0a]	286163	1			T1	1212		T2	69		T3	219
valid_sources[0x0b]	323373	1			T1	1089		T2	103		T3	245
valid_sources[0x0c]	288197	1			T1	1163		T2	80		T3	221
valid_sources[0x0d]	311013	1			T1	1150		T2	107		T3	197
valid_sources[0x0e]	281501	1			T1	1095		T2	95		T3	185
valid_sources[0x0f]	296899	1			T1	1199		T2	84		T3	169
valid_sources[0x10]	321731	1			T1	1188		T2	79		T3	196
valid_sources[0x11]	274031	1			T1	1084		T2	97		T3	208
valid_sources[0x12]	335530	1			T1	1416		T2	79		T3	164
valid_sources[0x13]	285081	1			T1	1154		T2	113		T3	193
valid_sources[0x14]	269999	1			T1	1061		T2	85		T3	176
valid_sources[0x15]	275919	1			T1	1250		T2	102		T3	181
valid_sources[0x16]	286023	1			T1	1362		T2	97		T3	226
valid_sources[0x17]	271324	1			T1	1233		T2	86		T3	181
valid_sources[0x18]	277189	1			T1	1273		T2	77		T3	203
valid_sources[0x19]	270587	1			T1	1149		T2	68		T3	221
valid_sources[0x1a]	288760	1			T1	1186		T2	86		T3	233
valid_sources[0x1b]	260500	1			T1	1186		T2	113		T3	197
valid_sources[0x1c]	299661	1			T1	1290		T2	79		T3	216
valid_sources[0x1d]	265614	1			T1	1406		T2	78		T3	172
valid_sources[0x1e]	295016	1			T1	1209		T2	82		T3	189
valid_sources[0x1f]	353536	1			T1	1184		T2	82		T3	207
valid_sources[0x20]	298574	1			T1	1236		T2	77		T3	209
valid_sources[0x21]	263698	1			T1	1353		T2	111		T3	213
valid_sources[0x22]	300715	1			T1	1088		T2	86		T3	206
valid_sources[0x23]	270513	1			T1	1219		T2	79		T3	216
valid_sources[0x24]	272840	1			T1	1172		T2	80		T3	206
valid_sources[0x25]	294309	1			T1	1182		T2	89		T3	200
valid_sources[0x26]	327806	1			T1	1208		T2	84		T3	189
valid_sources[0x27]	277548	1			T1	1234		T2	79		T3	227
valid_sources[0x28]	275247	1			T1	1098		T2	88		T3	171
valid_sources[0x29]	294921	1			T1	1233		T2	79		T3	197
valid_sources[0x2a]	277679	1			T1	1254		T2	111		T3	219
valid_sources[0x2b]	273891	1			T1	990		T2	105		T3	215
valid_sources[0x2c]	315919	1			T1	1005		T2	75		T3	182
valid_sources[0x2d]	307569	1			T1	1092		T2	89		T3	220
valid_sources[0x2e]	305976	1			T1	1377		T2	106		T3	190
valid_sources[0x2f]	285201	1			T1	1151		T2	66		T3	208
valid_sources[0x30]	286696	1			T1	1114		T2	102		T3	214
valid_sources[0x31]	271421	1			T1	1231		T2	91		T3	177
valid_sources[0x32]	311226	1			T1	1092		T2	94		T3	175
valid_sources[0x33]	262474	1			T1	1244		T2	94		T3	193
valid_sources[0x34]	330300	1			T1	1225		T2	103		T3	208
valid_sources[0x35]	268271	1			T1	1282		T2	82		T3	206
valid_sources[0x36]	275654	1			T1	1217		T2	80		T3	189
valid_sources[0x37]	323202	1			T1	1307		T2	98		T3	207
valid_sources[0x38]	344752	1			T1	1110		T2	124		T3	199
valid_sources[0x39]	276363	1			T1	1228		T2	86		T3	208
valid_sources[0x3a]	325122	1			T1	1330		T2	93		T3	175
valid_sources[0x3b]	311423	1			T1	1240		T2	89		T3	203
valid_sources[0x3c]	277730	1			T1	1338		T2	76		T3	206
valid_sources[0x3d]	308580	1			T1	1240		T2	88		T3	200
valid_sources[0x3e]	317015	1			T1	1184		T2	96		T3	191
valid_sources[0x3f]	273423	1			T1	1175		T2	101		T3	194
valid_sources[0x40]	325813	1			T1	1251		T2	65		T3	200
valid_sources[0x41]	336206	1			T1	1193		T2	58		T3	204
valid_sources[0x42]	277938	1			T1	1236		T2	77		T3	196
valid_sources[0x43]	277586	1			T1	1156		T2	99		T3	202
valid_sources[0x44]	281202	1			T1	1133		T2	89		T3	205
valid_sources[0x45]	317182	1			T1	1247		T2	78		T3	215
valid_sources[0x46]	308343	1			T1	1295		T2	95		T3	189
valid_sources[0x47]	337691	1			T1	1388		T2	95		T3	189
valid_sources[0x48]	330714	1			T1	1272		T2	85		T3	201
valid_sources[0x49]	305590	1			T1	1215		T2	93		T3	204
valid_sources[0x4a]	332366	1			T1	1339		T2	78		T3	203
valid_sources[0x4b]	290201	1			T1	1205		T2	79		T3	225
valid_sources[0x4c]	284215	1			T1	1234		T2	106		T3	198
valid_sources[0x4d]	296434	1			T1	1303		T2	90		T3	215
valid_sources[0x4e]	295344	1			T1	1195		T2	100		T3	210
valid_sources[0x4f]	326241	1			T1	1368		T2	80		T3	204
valid_sources[0x50]	312004	1			T1	1381		T2	103		T3	196
valid_sources[0x51]	307074	1			T1	1198		T2	92		T3	212
valid_sources[0x52]	298716	1			T1	1173		T2	74		T3	209
valid_sources[0x53]	335173	1			T1	1073		T2	102		T3	171
valid_sources[0x54]	302670	1			T1	1333		T2	109		T3	192
valid_sources[0x55]	288996	1			T1	1202		T2	97		T3	171
valid_sources[0x56]	337287	1			T1	1195		T2	96		T3	163
valid_sources[0x57]	352533	1			T1	1350		T2	87		T3	201
valid_sources[0x58]	289233	1			T1	1095		T2	113		T3	241
valid_sources[0x59]	315259	1			T1	1211		T2	72		T3	185
valid_sources[0x5a]	296250	1			T1	1394		T2	91		T3	195
valid_sources[0x5b]	273886	1			T1	1091		T2	101		T3	190
valid_sources[0x5c]	294496	1			T1	1182		T2	74		T3	219
valid_sources[0x5d]	296390	1			T1	1467		T2	83		T3	191
valid_sources[0x5e]	291806	1			T1	1304		T2	79		T3	203
valid_sources[0x5f]	290657	1			T1	1251		T2	81		T3	167
valid_sources[0x60]	306771	1			T1	1296		T2	86		T3	199
valid_sources[0x61]	281991	1			T1	1127		T2	99		T3	186
valid_sources[0x62]	286753	1			T1	1215		T2	67		T3	234
valid_sources[0x63]	317878	1			T1	1244		T2	98		T3	199
valid_sources[0x64]	348970	1			T1	1086		T2	78		T3	198
valid_sources[0x65]	289607	1			T1	1134		T2	94		T3	200
valid_sources[0x66]	276716	1			T1	1274		T2	83		T3	207
valid_sources[0x67]	270630	1			T1	1255		T2	66		T3	201
valid_sources[0x68]	339321	1			T1	1170		T2	96		T3	185
valid_sources[0x69]	336718	1			T1	1151		T2	67		T3	247
valid_sources[0x6a]	260083	1			T1	1128		T2	89		T3	206
valid_sources[0x6b]	277975	1			T1	1302		T2	86		T3	194
valid_sources[0x6c]	332159	1			T1	1165		T2	85		T3	220
valid_sources[0x6d]	315333	1			T1	1183		T2	82		T3	179
valid_sources[0x6e]	278443	1			T1	1210		T2	99		T3	208
valid_sources[0x6f]	270052	1			T1	1239		T2	96		T3	199
valid_sources[0x70]	337160	1			T1	1341		T2	77		T3	179
valid_sources[0x71]	329407	1			T1	1231		T2	79		T3	200
valid_sources[0x72]	315240	1			T1	1167		T2	90		T3	202
valid_sources[0x73]	281115	1			T1	1286		T2	82		T3	203
valid_sources[0x74]	267020	1			T1	1237		T2	89		T3	231
valid_sources[0x75]	260799	1			T1	1375		T2	102		T3	210
valid_sources[0x76]	288381	1			T1	1176		T2	78		T3	211
valid_sources[0x77]	284836	1			T1	1163		T2	83		T3	191
valid_sources[0x78]	314908	1			T1	1199		T2	81		T3	189
valid_sources[0x79]	258095	1			T1	1162		T2	60		T3	214
valid_sources[0x7a]	382040	1			T1	1234		T2	84		T3	207
valid_sources[0x7b]	282622	1			T1	1279		T2	92		T3	223
valid_sources[0x7c]	292474	1			T1	1141		T2	74		T3	227
valid_sources[0x7d]	360839	1			T1	1176		T2	98		T3	206
valid_sources[0x7e]	273151	1			T1	1324		T2	109		T3	156
valid_sources[0x7f]	341698	1			T1	1184		T2	112		T3	211
valid_sources[0x80]	280328	1			T1	1176		T2	96		T3	210

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30554845

1

T1

28091

T2

11264

T3

25600

values[0x0]

all_enables

biggest_size

15388531

1

T1

14154

T2

5662

T3

12797

values[0x1]

all_enables

biggest_size

15387252

1

T1

14083

T2

5602

T3

12803

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141944

1

T1

2

T2

4

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52445	1			T4	22		T5	17		T10	15
values[0x0]	61335	1			T1	3		T2	7		T3	10
values[0x1]	66497	1			T1	3		T2	4		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151454

1

T1

3

T2

4

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	748	1			T4	2		T23	6		T21	1
valid_sources[0x01]	627	1			T2	2		T14	1		T20	2
valid_sources[0x02]	1206	1			T10	2		T23	10		T25	5
valid_sources[0x03]	613	1			T10	2		T23	12		T24	24
valid_sources[0x04]	601	1			T23	4		T24	16		T25	17
valid_sources[0x05]	845	1			T4	1		T5	1		T10	1
valid_sources[0x06]	655	1			T4	2		T5	1		T10	1
valid_sources[0x07]	517	1			T23	2		T71	1		T21	1
valid_sources[0x08]	579	1			T23	24		T81	34		T24	25
valid_sources[0x09]	841	1			T4	2		T43	1		T6	6
valid_sources[0x0a]	709	1			T20	1		T6	5		T23	12
valid_sources[0x0b]	498	1			T23	9		T21	1		T8	1
valid_sources[0x0c]	671	1			T6	4		T23	15		T21	1
valid_sources[0x0d]	626	1			T20	1		T23	5		T21	1
valid_sources[0x0e]	670	1			T4	1		T23	14		T19	1
valid_sources[0x0f]	925	1			T10	2		T23	9		T24	13
valid_sources[0x10]	560	1			T4	1		T23	8		T24	1
valid_sources[0x11]	675	1			T5	1		T10	1		T23	4
valid_sources[0x12]	899	1			T23	5		T21	1		T24	13
valid_sources[0x13]	607	1			T46	1		T23	11		T21	1
valid_sources[0x14]	639	1			T5	1		T20	1		T60	2
valid_sources[0x15]	814	1			T6	3		T23	10		T71	1
valid_sources[0x16]	526	1			T5	1		T61	1		T43	3
valid_sources[0x17]	657	1			T10	1		T14	1		T23	17
valid_sources[0x18]	498	1			T23	18		T8	1		T24	20
valid_sources[0x19]	808	1			T23	10		T71	3		T140	1
valid_sources[0x1a]	949	1			T23	6		T71	2		T8	1
valid_sources[0x1b]	538	1			T43	1		T23	15		T24	36
valid_sources[0x1c]	785	1			T4	2		T23	11		T24	9
valid_sources[0x1d]	540	1			T10	1		T20	2		T23	30
valid_sources[0x1e]	483	1			T4	1		T5	1		T20	2
valid_sources[0x1f]	798	1			T5	2		T46	1		T23	12
valid_sources[0x20]	527	1			T10	1		T59	4		T23	12
valid_sources[0x21]	636	1			T10	1		T23	17		T24	14
valid_sources[0x22]	530	1			T4	9		T23	12		T71	1
valid_sources[0x23]	602	1			T4	3		T10	2		T46	1
valid_sources[0x24]	627	1			T4	5		T10	2		T23	10
valid_sources[0x25]	920	1			T23	14		T19	1		T24	29
valid_sources[0x26]	662	1			T5	1		T23	14		T71	1
valid_sources[0x27]	769	1			T61	1		T23	10		T75	2
valid_sources[0x28]	691	1			T57	7		T23	4		T24	28
valid_sources[0x29]	536	1			T5	2		T141	1		T23	2
valid_sources[0x2a]	471	1			T23	15		T75	1		T19	1
valid_sources[0x2b]	757	1			T4	5		T23	4		T7	5
valid_sources[0x2c]	713	1			T5	1		T10	1		T23	4
valid_sources[0x2d]	483	1			T5	1		T20	3		T23	14
valid_sources[0x2e]	640	1			T23	7		T7	1		T24	28
valid_sources[0x2f]	581	1			T10	1		T12	1		T23	3
valid_sources[0x30]	527	1			T5	1		T61	1		T23	14
valid_sources[0x31]	583	1			T4	2		T10	1		T14	1
valid_sources[0x32]	488	1			T23	7		T24	4		T25	7
valid_sources[0x33]	743	1			T10	1		T20	1		T23	15
valid_sources[0x34]	748	1			T5	1		T10	1		T23	19
valid_sources[0x35]	999	1			T4	4		T5	4		T10	1
valid_sources[0x36]	564	1			T4	6		T23	3		T21	1
valid_sources[0x37]	716	1			T4	1		T10	1		T23	6
valid_sources[0x38]	664	1			T4	1		T5	2		T14	1
valid_sources[0x39]	1015	1			T40	2		T20	1		T23	3
valid_sources[0x3a]	900	1			T20	3		T44	32		T23	15
valid_sources[0x3b]	1074	1			T4	2		T20	1		T141	2
valid_sources[0x3c]	523	1			T14	1		T23	17		T71	1
valid_sources[0x3d]	920	1			T20	1		T23	10		T21	1
valid_sources[0x3e]	738	1			T46	1		T23	7		T21	1
valid_sources[0x3f]	588	1			T4	5		T23	7		T71	4
valid_sources[0x40]	559	1			T4	2		T61	1		T23	26
valid_sources[0x41]	485	1			T4	2		T12	1		T23	10
valid_sources[0x42]	861	1			T4	2		T10	1		T23	2
valid_sources[0x43]	1009	1			T4	1		T23	13		T19	1
valid_sources[0x44]	691	1			T10	1		T23	13		T24	6
valid_sources[0x45]	706	1			T4	1		T20	3		T23	7
valid_sources[0x46]	611	1			T41	2		T23	2		T24	5
valid_sources[0x47]	881	1			T4	2		T6	3		T23	14
valid_sources[0x48]	721	1			T23	14		T24	6		T22	2
valid_sources[0x49]	768	1			T5	1		T23	8		T71	2
valid_sources[0x4a]	495	1			T10	2		T20	1		T23	24
valid_sources[0x4b]	838	1			T23	10		T71	1		T7	2
valid_sources[0x4c]	633	1			T10	1		T23	3		T24	31
valid_sources[0x4d]	526	1			T4	3		T12	1		T23	17
valid_sources[0x4e]	517	1			T4	2		T10	1		T12	1
valid_sources[0x4f]	509	1			T23	1		T71	1		T21	2
valid_sources[0x50]	670	1			T4	1		T23	5		T21	1
valid_sources[0x51]	900	1			T23	1		T75	1		T21	1
valid_sources[0x52]	628	1			T10	1		T12	1		T46	2
valid_sources[0x53]	561	1			T4	2		T10	1		T6	13
valid_sources[0x54]	560	1			T5	1		T23	6		T24	2
valid_sources[0x55]	900	1			T4	4		T20	2		T23	7
valid_sources[0x56]	557	1			T23	21		T19	1		T24	2
valid_sources[0x57]	616	1			T20	3		T23	6		T21	2
valid_sources[0x58]	682	1			T5	1		T20	1		T23	6
valid_sources[0x59]	521	1			T23	12		T21	1		T19	1
valid_sources[0x5a]	645	1			T5	1		T23	26		T75	1
valid_sources[0x5b]	834	1			T10	1		T23	16		T71	2
valid_sources[0x5c]	823	1			T10	1		T14	1		T20	1
valid_sources[0x5d]	494	1			T20	1		T23	7		T24	6
valid_sources[0x5e]	528	1			T5	1		T20	1		T23	12
valid_sources[0x5f]	583	1			T23	9		T24	7		T25	9
valid_sources[0x60]	711	1			T23	12		T21	1		T24	21
valid_sources[0x61]	731	1			T4	6		T5	1		T23	3
valid_sources[0x62]	737	1			T5	3		T61	1		T23	7
valid_sources[0x63]	799	1			T4	5		T20	1		T23	32
valid_sources[0x64]	1114	1			T23	17		T21	1		T140	2
valid_sources[0x65]	595	1			T23	3		T21	1		T8	1
valid_sources[0x66]	861	1			T4	2		T10	1		T23	8
valid_sources[0x67]	570	1			T5	1		T20	1		T23	17
valid_sources[0x68]	706	1			T23	16		T21	1		T19	1
valid_sources[0x69]	564	1			T23	12		T71	1		T25	3
valid_sources[0x6a]	656	1			T4	1		T23	11		T7	1
valid_sources[0x6b]	1174	1			T23	2		T24	25		T25	11
valid_sources[0x6c]	848	1			T10	1		T20	1		T23	31
valid_sources[0x6d]	493	1			T2	3		T23	9		T71	3
valid_sources[0x6e]	650	1			T12	1		T58	3		T67	3
valid_sources[0x6f]	766	1			T5	1		T10	3		T141	1
valid_sources[0x70]	764	1			T1	2		T4	2		T141	1
valid_sources[0x71]	578	1			T23	10		T21	1		T24	36
valid_sources[0x72]	689	1			T23	9		T22	1		T25	13
valid_sources[0x73]	878	1			T61	1		T23	5		T24	4
valid_sources[0x74]	558	1			T10	1		T12	1		T61	1
valid_sources[0x75]	533	1			T23	5		T71	1		T55	1
valid_sources[0x76]	545	1			T4	1		T10	2		T14	1
valid_sources[0x77]	710	1			T12	1		T23	5		T136	3
valid_sources[0x78]	893	1			T14	1		T23	13		T24	8
valid_sources[0x79]	488	1			T10	1		T24	27		T136	1
valid_sources[0x7a]	847	1			T20	1		T43	3		T23	24
valid_sources[0x7b]	778	1			T23	2		T24	53		T25	5
valid_sources[0x7c]	723	1			T14	1		T20	1		T23	10
valid_sources[0x7d]	988	1			T10	1		T23	12		T75	2
valid_sources[0x7e]	612	1			T4	1		T5	2		T10	1
valid_sources[0x7f]	577	1			T20	1		T23	1		T24	9
valid_sources[0x80]	559	1			T4	4		T23	10		T24	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39065

1

T4

14

T5

8

T10

8

values[0x0]

all_enables

biggest_size

52483

1

T1

2

T2

4

T3

2

values[0x1]

all_enables

biggest_size

50396

1

T3

3

T4

13

T5

8