Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14633493

1

T1

254419

T4

59418

T5

14663

full_word

55824245

1

T1

56328

T2

22528

T3

51200

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70457428	1			T1	310747		T2	22528		T3	51200
auto[TlIntgErrCmd]	123	1			T68	5		T69	4		T70	11
auto[TlIntgErrData]	72	1			T69	4		T70	3		T121	6
auto[TlIntgErrBoth]	115	1			T68	5		T69	2		T70	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32120315

1

T1

155311

T2

11264

T3

25600

auto[1]

38337423

1

T1

155436

T2

11264

T3

25600

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6984397	1			T1	127220		T4	23825		T5	5404
auto[TlIntgErrNone]	partial	auto[1]	7648820	1			T1	127199		T4	35593		T5	9259
auto[TlIntgErrNone]	full_word	auto[0]	25135782	1			T1	28091		T2	11264		T3	25600
auto[TlIntgErrNone]	full_word	auto[1]	30688429	1			T1	28237		T2	11264		T3	25600
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T70	2		T121	3		T124	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T68	4		T69	2		T70	9
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T69	2		T124	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T68	1		T130	2		T123	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T69	2		T70	1		T121	4
auto[TlIntgErrData]	partial	auto[1]	31	1			T69	2		T70	2		T121	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T121	1		T122	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T131	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T68	2		T121	4		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T68	3		T69	2		T70	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T132	1		T127	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T129	1		T132	1		T123	1