Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	753130	1			T1	18112		T4	300		T5	29
auto[1]	10432761	1			T1	19312		T4	3254		T5	427
auto[2]	616034	1			T1	16148		T4	247		T5	30
auto[3]	10298940	1			T1	17457		T4	3183		T5	425

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14352607	1			T1	1533		T4	4998		T5	626
auto[1]	2096163	1			T1	8078		T4	730		T5	95
auto[2]	2114447	1			T1	9878		T4	1133		T5	170
auto[3]	3537648	1			T1	51540		T4	123		T5	20

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8596340

1

T1

12

T4

6975

T5

910

auto[1]

13504525

1

T1

71017

T4

9

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	213954	1			T4	254		T5	24		T9	762
auto[0]	auto[0]	auto[1]	21886	1			T1	1		T4	21		T5	3
auto[0]	auto[0]	auto[2]	21977	1			T4	23		T5	1		T9	82
auto[0]	auto[0]	auto[3]	6224	1			T1	3		T4	2		T5	1
auto[0]	auto[1]	auto[0]	3333874	1			T4	2497		T5	310		T9	94
auto[0]	auto[1]	auto[1]	341185	1			T1	1		T4	448		T5	69
auto[0]	auto[1]	auto[2]	335870	1			T4	254		T5	37		T9	6
auto[0]	auto[1]	auto[3]	61754	1			T1	2		T4	51		T5	10
auto[0]	auto[2]	auto[0]	179425	1			T9	697		T41	1		T75	162
auto[0]	auto[2]	auto[1]	18373	1			T9	67		T75	11		T21	85
auto[0]	auto[2]	auto[2]	21243	1			T4	227		T5	30		T9	63
auto[0]	auto[2]	auto[3]	5091	1			T1	1		T4	20		T9	6
auto[0]	auto[3]	auto[0]	3299448	1			T4	2242		T5	291		T9	58
auto[0]	auto[3]	auto[1]	331839	1			T4	259		T5	23		T9	6
auto[0]	auto[3]	auto[2]	340847	1			T1	2		T4	628		T5	102
auto[0]	auto[3]	auto[3]	63350	1			T1	2		T4	49		T5	9
auto[1]	auto[0]	auto[0]	16453	1			T1	627		T9	1		T41	460
auto[1]	auto[0]	auto[1]	72941	1			T1	2661		T41	2276		T59	650
auto[1]	auto[0]	auto[2]	72479	1			T1	2668		T41	2279		T59	662
auto[1]	auto[0]	auto[3]	327216	1			T1	12152		T41	10307		T59	2967
auto[1]	auto[1]	auto[0]	3652074	1			T1	383		T4	4		T5	1
auto[1]	auto[1]	auto[1]	653036	1			T1	3020		T13	10664		T41	2334
auto[1]	auto[1]	auto[2]	622254	1			T1	1805		T13	10550		T41	379
auto[1]	auto[1]	auto[3]	1432714	1			T1	14101		T13	1080		T41	10364
auto[1]	auto[2]	auto[0]	12016	1			T1	358		T41	465		T21	1
auto[1]	auto[2]	auto[1]	53633	1			T1	1687		T41	2115		T137	1
auto[1]	auto[2]	auto[2]	59538	1			T1	2506		T41	1508		T59	604
auto[1]	auto[2]	auto[3]	266715	1			T1	11596		T41	6922		T59	2656
auto[1]	auto[3]	auto[0]	3645363	1			T1	165		T4	1		T13	106230
auto[1]	auto[3]	auto[1]	603270	1			T1	708		T4	2		T13	10596
auto[1]	auto[3]	auto[2]	640239	1			T1	2897		T4	1		T13	10631
auto[1]	auto[3]	auto[3]	1374584	1			T1	13683		T4	1		T13	1039