Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	327542456	218572	0	0
ctrl_regwen_rd_A	327542456	3857	0	0
exec_rd_A	327542456	3532	0	0
exec_regwen_rd_A	327542456	3908	0	0
readback_rd_A	327542456	2544	0	0
readback_regwen_rd_A	327542456	2279	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327542456	218572	0	0
T7	63601	0	0	0
T15	1397	0	0	0
T23	179249	4443	0	0
T24	0	5060	0	0
T25	0	2680	0	0
T63	0	3090	0	0
T66	0	5884	0	0
T71	118894	0	0	0
T75	239383	0	0	0
T76	0	5228	0	0
T77	0	1271	0	0
T78	0	8514	0	0
T79	0	1768	0	0
T80	0	4297	0	0
T81	281392	0	0	0
T82	18022	0	0	0
T83	213517	0	0	0
T84	347364	0	0	0
T85	79499	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327542456	3857	0	0
T7	63601	0	0	0
T15	1397	0	0	0
T23	179249	198	0	0
T24	0	364	0	0
T25	0	254	0	0
T49	0	235	0	0
T51	0	324	0	0
T71	118894	0	0	0
T75	239383	0	0	0
T81	281392	0	0	0
T82	18022	0	0	0
T83	213517	0	0	0
T84	347364	0	0	0
T85	79499	0	0	0
T114	0	174	0	0
T115	0	203	0	0
T116	0	136	0	0
T117	0	188	0	0
T118	0	114	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327542456	3532	0	0
T7	63601	0	0	0
T15	1397	0	0	0
T23	179249	183	0	0
T24	0	259	0	0
T25	0	222	0	0
T49	0	286	0	0
T51	0	335	0	0
T71	118894	0	0	0
T75	239383	0	0	0
T81	281392	0	0	0
T82	18022	0	0	0
T83	213517	0	0	0
T84	347364	0	0	0
T85	79499	0	0	0
T114	0	140	0	0
T115	0	176	0	0
T116	0	97	0	0
T117	0	176	0	0
T118	0	58	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327542456	3908	0	0
T7	63601	0	0	0
T15	1397	0	0	0
T23	179249	170	0	0
T24	0	354	0	0
T25	0	324	0	0
T49	0	309	0	0
T51	0	302	0	0
T71	118894	0	0	0
T75	239383	0	0	0
T81	281392	0	0	0
T82	18022	0	0	0
T83	213517	0	0	0
T84	347364	0	0	0
T85	79499	0	0	0
T114	0	183	0	0
T115	0	214	0	0
T116	0	144	0	0
T117	0	223	0	0
T118	0	80	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327542456	2544	0	0
T7	63601	0	0	0
T15	1397	0	0	0
T23	179249	177	0	0
T24	0	369	0	0
T25	0	204	0	0
T49	0	245	0	0
T51	0	314	0	0
T71	118894	0	0	0
T75	239383	0	0	0
T81	281392	0	0	0
T82	18022	0	0	0
T83	213517	0	0	0
T84	347364	0	0	0
T85	79499	0	0	0
T114	0	161	0	0
T115	0	242	0	0
T116	0	125	0	0
T117	0	135	0	0
T118	0	79	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327542456	2279	0	0
T7	63601	0	0	0
T15	1397	0	0	0
T23	179249	203	0	0
T24	0	241	0	0
T25	0	188	0	0
T49	0	234	0	0
T51	0	372	0	0
T71	118894	0	0	0
T75	239383	0	0	0
T81	281392	0	0	0
T82	18022	0	0	0
T83	213517	0	0	0
T84	347364	0	0	0
T85	79499	0	0	0
T114	0	123	0	0
T115	0	101	0	0
T116	0	87	0	0
T117	0	207	0	0
T118	0	126	0	0