Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14197577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57989345

1

T2

1680

T3

4442

T4

349422

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35982167	1			T2	911		T3	2726		T4	188952
values[0x0]	16678332	1			T2	476		T3	1257		T4	91350
values[0x1]	19526423	1			T2	472		T3	1414		T4	96719

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7073167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65113755

1

T2

1767

T3

4924

T4

363178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	270187	1			T2	4		T3	23		T4	3059
valid_sources[0x01]	258036	1			T2	8		T3	20		T4	1334
valid_sources[0x02]	314198	1			T2	10		T3	14		T4	1440
valid_sources[0x03]	327184	1			T2	9		T3	23		T4	1312
valid_sources[0x04]	310813	1			T2	3		T3	27		T4	2408
valid_sources[0x05]	277843	1			T2	5		T3	27		T4	1204
valid_sources[0x06]	326672	1			T2	5		T3	19		T4	1902
valid_sources[0x07]	250649	1			T2	6		T3	27		T4	1085
valid_sources[0x08]	274153	1			T2	6		T3	23		T4	1254
valid_sources[0x09]	280783	1			T2	4		T3	17		T4	1953
valid_sources[0x0a]	276712	1			T2	5		T3	22		T4	1533
valid_sources[0x0b]	286150	1			T2	8		T3	22		T4	1167
valid_sources[0x0c]	265758	1			T2	1		T3	18		T4	1431
valid_sources[0x0d]	270671	1			T2	6		T3	21		T4	922
valid_sources[0x0e]	295483	1			T2	6		T3	18		T4	927
valid_sources[0x0f]	328183	1			T2	11		T3	26		T4	1351
valid_sources[0x10]	266482	1			T2	16		T3	22		T4	1446
valid_sources[0x11]	273619	1			T2	8		T3	28		T4	1792
valid_sources[0x12]	269006	1			T2	15		T3	32		T4	1435
valid_sources[0x13]	287897	1			T2	17		T3	29		T4	1230
valid_sources[0x14]	270821	1			T2	18		T3	19		T4	2347
valid_sources[0x15]	281424	1			T2	5		T3	18		T4	1358
valid_sources[0x16]	318145	1			T2	3		T3	22		T4	871
valid_sources[0x17]	347769	1			T2	5		T3	20		T4	1328
valid_sources[0x18]	264794	1			T2	4		T3	18		T4	2342
valid_sources[0x19]	276345	1			T2	13		T3	24		T4	2013
valid_sources[0x1a]	289579	1			T2	4		T3	24		T4	1648
valid_sources[0x1b]	250008	1			T2	5		T3	20		T4	1575
valid_sources[0x1c]	278422	1			T2	9		T3	14		T4	1773
valid_sources[0x1d]	255300	1			T2	5		T3	15		T4	1831
valid_sources[0x1e]	268963	1			T2	11		T3	22		T4	2128
valid_sources[0x1f]	254558	1			T2	4		T3	18		T4	1636
valid_sources[0x20]	278774	1			T2	10		T3	18		T4	1205
valid_sources[0x21]	268299	1			T2	6		T3	16		T4	2056
valid_sources[0x22]	286725	1			T2	9		T3	19		T4	988
valid_sources[0x23]	289290	1			T2	2		T3	33		T4	1931
valid_sources[0x24]	319213	1			T2	3		T3	20		T4	1464
valid_sources[0x25]	275731	1			T2	4		T3	18		T4	947
valid_sources[0x26]	290699	1			T2	3		T3	20		T4	1636
valid_sources[0x27]	271013	1			T2	9		T3	25		T4	464
valid_sources[0x28]	272175	1			T2	4		T3	15		T4	1459
valid_sources[0x29]	289439	1			T2	9		T3	15		T4	1118
valid_sources[0x2a]	249050	1			T2	5		T3	20		T4	1896
valid_sources[0x2b]	283207	1			T2	4		T3	23		T4	2200
valid_sources[0x2c]	254355	1			T2	8		T3	25		T4	1685
valid_sources[0x2d]	271202	1			T2	8		T3	22		T4	1206
valid_sources[0x2e]	252248	1			T2	6		T3	23		T4	1046
valid_sources[0x2f]	247007	1			T2	8		T3	20		T4	1499
valid_sources[0x30]	306435	1			T2	7		T3	20		T4	1086
valid_sources[0x31]	375206	1			T2	5		T3	19		T4	303
valid_sources[0x32]	302937	1			T2	2		T3	17		T4	1259
valid_sources[0x33]	281923	1			T2	14		T3	26		T4	1171
valid_sources[0x34]	291872	1			T2	13		T3	24		T4	1752
valid_sources[0x35]	267557	1			T2	3		T3	20		T4	2112
valid_sources[0x36]	243046	1			T2	2		T3	18		T4	1150
valid_sources[0x37]	366128	1			T2	5		T3	23		T4	1303
valid_sources[0x38]	267948	1			T2	5		T3	22		T4	1093
valid_sources[0x39]	294886	1			T2	4		T3	17		T4	2278
valid_sources[0x3a]	283422	1			T2	6		T3	22		T4	1729
valid_sources[0x3b]	265719	1			T2	12		T3	18		T4	516
valid_sources[0x3c]	246371	1			T2	2		T3	19		T4	1600
valid_sources[0x3d]	291757	1			T2	9		T3	27		T4	1772
valid_sources[0x3e]	267491	1			T2	6		T3	28		T4	1989
valid_sources[0x3f]	249074	1			T2	16		T3	16		T4	1949
valid_sources[0x40]	304485	1			T2	13		T3	20		T4	1678
valid_sources[0x41]	252594	1			T2	8		T3	28		T4	1049
valid_sources[0x42]	286870	1			T2	6		T3	18		T4	1116
valid_sources[0x43]	272883	1			T2	1		T3	19		T4	1061
valid_sources[0x44]	261934	1			T2	11		T3	17		T4	1031
valid_sources[0x45]	273397	1			T3	12		T4	1602		T5	14
valid_sources[0x46]	303400	1			T2	16		T3	16		T4	1313
valid_sources[0x47]	307012	1			T2	11		T3	16		T4	1237
valid_sources[0x48]	246438	1			T2	10		T3	20		T4	644
valid_sources[0x49]	261737	1			T2	8		T3	25		T4	838
valid_sources[0x4a]	274233	1			T2	13		T3	15		T4	1272
valid_sources[0x4b]	250037	1			T2	7		T3	25		T4	1470
valid_sources[0x4c]	272989	1			T2	13		T3	24		T4	2030
valid_sources[0x4d]	244445	1			T2	6		T3	18		T4	943
valid_sources[0x4e]	302883	1			T2	4		T3	30		T4	1851
valid_sources[0x4f]	298795	1			T2	11		T3	25		T4	750
valid_sources[0x50]	296931	1			T2	6		T3	26		T4	1485
valid_sources[0x51]	270489	1			T2	4		T3	22		T4	1465
valid_sources[0x52]	270826	1			T2	2		T3	29		T4	1692
valid_sources[0x53]	243392	1			T2	9		T3	28		T4	2217
valid_sources[0x54]	309999	1			T2	4		T3	25		T4	1917
valid_sources[0x55]	297924	1			T2	16		T3	23		T4	759
valid_sources[0x56]	251592	1			T2	5		T3	19		T4	2073
valid_sources[0x57]	364243	1			T2	3		T3	22		T4	1119
valid_sources[0x58]	241789	1			T2	8		T3	27		T4	1180
valid_sources[0x59]	276042	1			T2	8		T3	31		T4	1968
valid_sources[0x5a]	241524	1			T2	10		T3	18		T4	774
valid_sources[0x5b]	268580	1			T2	3		T3	20		T4	1363
valid_sources[0x5c]	271744	1			T2	19		T3	16		T4	1545
valid_sources[0x5d]	274693	1			T2	9		T3	16		T4	2687
valid_sources[0x5e]	236945	1			T2	8		T3	15		T4	1073
valid_sources[0x5f]	283184	1			T2	2		T3	27		T4	798
valid_sources[0x60]	291732	1			T2	6		T3	24		T4	2270
valid_sources[0x61]	267480	1			T2	8		T3	23		T4	1945
valid_sources[0x62]	268998	1			T2	14		T3	28		T4	1605
valid_sources[0x63]	264215	1			T2	6		T3	22		T4	932
valid_sources[0x64]	259287	1			T2	4		T3	15		T4	1237
valid_sources[0x65]	299246	1			T2	7		T3	23		T4	1446
valid_sources[0x66]	259754	1			T2	7		T3	23		T4	1064
valid_sources[0x67]	336393	1			T3	18		T4	868		T5	9
valid_sources[0x68]	320221	1			T2	8		T3	25		T4	1290
valid_sources[0x69]	304873	1			T2	7		T3	19		T4	1488
valid_sources[0x6a]	248041	1			T2	12		T3	25		T4	1631
valid_sources[0x6b]	267570	1			T2	3		T3	26		T4	691
valid_sources[0x6c]	252033	1			T2	18		T3	29		T4	1160
valid_sources[0x6d]	274240	1			T2	8		T3	27		T4	2271
valid_sources[0x6e]	256161	1			T2	2		T3	22		T4	967
valid_sources[0x6f]	260839	1			T2	12		T3	23		T4	1763
valid_sources[0x70]	251476	1			T2	9		T3	26		T4	1124
valid_sources[0x71]	257687	1			T2	6		T3	21		T4	1187
valid_sources[0x72]	238709	1			T2	4		T3	22		T4	2066
valid_sources[0x73]	272318	1			T2	5		T3	22		T4	1036
valid_sources[0x74]	385708	1			T2	2		T3	17		T4	2142
valid_sources[0x75]	257884	1			T2	1		T3	19		T4	554
valid_sources[0x76]	272681	1			T2	5		T3	25		T4	3003
valid_sources[0x77]	310194	1			T2	3		T3	32		T4	2360
valid_sources[0x78]	244316	1			T2	3		T3	29		T4	2395
valid_sources[0x79]	248066	1			T2	17		T3	18		T4	1525
valid_sources[0x7a]	257702	1			T2	13		T3	9		T4	547
valid_sources[0x7b]	260347	1			T2	5		T3	18		T4	749
valid_sources[0x7c]	356415	1			T2	3		T3	12		T4	1477
valid_sources[0x7d]	273369	1			T2	8		T3	17		T4	1387
valid_sources[0x7e]	276414	1			T2	3		T3	16		T4	1788
valid_sources[0x7f]	280329	1			T2	2		T3	23		T4	1770
valid_sources[0x80]	265025	1			T2	6		T3	20		T4	1504

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28888187

1

T2

814

T3

2270

T4

175097

values[0x0]

all_enables

biggest_size

14546044

1

T2

455

T3

1108

T4

87272

values[0x1]

all_enables

biggest_size

14555114

1

T2

411

T3

1064

T4

87053

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134720

1

T1

1

T4

54

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49294	1			T4	32		T7	55		T19	17
values[0x0]	58339	1			T1	1		T3	1		T4	53
values[0x1]	61934	1			T2	1		T3	1		T4	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143182

1

T1

1

T4

65

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1039	1			T23	13		T24	23		T69	1
valid_sources[0x01]	648	1			T65	1		T23	16		T24	22
valid_sources[0x02]	820	1			T14	1		T23	15		T24	8
valid_sources[0x03]	800	1			T23	36		T74	3		T45	1
valid_sources[0x04]	505	1			T23	8		T24	31		T25	2
valid_sources[0x05]	622	1			T23	3		T24	12		T69	1
valid_sources[0x06]	855	1			T23	15		T24	13		T25	9
valid_sources[0x07]	597	1			T23	18		T45	1		T24	12
valid_sources[0x08]	577	1			T23	10		T68	1		T24	17
valid_sources[0x09]	503	1			T23	14		T24	8		T69	1
valid_sources[0x0a]	670	1			T23	24		T143	2		T24	14
valid_sources[0x0b]	869	1			T23	5		T143	3		T24	21
valid_sources[0x0c]	984	1			T23	6		T24	28		T25	8
valid_sources[0x0d]	632	1			T23	37		T24	23		T25	4
valid_sources[0x0e]	921	1			T12	1		T7	167		T23	6
valid_sources[0x0f]	630	1			T23	23		T24	8		T25	5
valid_sources[0x10]	761	1			T23	14		T24	14		T25	4
valid_sources[0x11]	528	1			T23	15		T24	7		T25	4
valid_sources[0x12]	959	1			T2	1		T23	12		T68	1
valid_sources[0x13]	601	1			T23	7		T147	1		T24	7
valid_sources[0x14]	515	1			T1	1		T4	4		T23	1
valid_sources[0x15]	585	1			T23	11		T79	1		T24	10
valid_sources[0x16]	995	1			T23	23		T143	1		T24	13
valid_sources[0x17]	524	1			T23	19		T49	3		T68	1
valid_sources[0x18]	605	1			T23	13		T45	2		T143	1
valid_sources[0x19]	518	1			T42	2		T23	30		T148	2
valid_sources[0x1a]	921	1			T23	22		T147	3		T24	9
valid_sources[0x1b]	620	1			T23	21		T24	23		T25	4
valid_sources[0x1c]	523	1			T4	11		T149	6		T23	9
valid_sources[0x1d]	530	1			T23	19		T24	17		T25	5
valid_sources[0x1e]	717	1			T23	26		T45	5		T147	2
valid_sources[0x1f]	475	1			T23	1		T24	17		T25	6
valid_sources[0x20]	604	1			T18	1		T65	1		T23	8
valid_sources[0x21]	627	1			T23	26		T68	1		T24	25
valid_sources[0x22]	613	1			T23	16		T24	32		T25	7
valid_sources[0x23]	564	1			T23	2		T24	11		T25	4
valid_sources[0x24]	497	1			T23	10		T24	5		T69	2
valid_sources[0x25]	551	1			T23	17		T45	7		T24	16
valid_sources[0x26]	537	1			T23	19		T45	1		T24	8
valid_sources[0x27]	700	1			T23	16		T24	16		T69	1
valid_sources[0x28]	659	1			T11	1		T23	23		T24	11
valid_sources[0x29]	633	1			T23	12		T24	10		T25	2
valid_sources[0x2a]	564	1			T23	12		T68	3		T24	14
valid_sources[0x2b]	532	1			T23	30		T24	13		T69	1
valid_sources[0x2c]	512	1			T3	2		T150	1		T23	28
valid_sources[0x2d]	657	1			T23	9		T24	13		T25	5
valid_sources[0x2e]	530	1			T13	1		T23	20		T68	1
valid_sources[0x2f]	621	1			T42	2		T23	6		T79	1
valid_sources[0x30]	935	1			T65	1		T23	36		T24	23
valid_sources[0x31]	587	1			T42	4		T23	5		T68	1
valid_sources[0x32]	513	1			T23	6		T24	16		T25	6
valid_sources[0x33]	605	1			T23	16		T80	1		T143	1
valid_sources[0x34]	828	1			T19	130		T23	13		T45	1
valid_sources[0x35]	541	1			T23	16		T24	13		T69	2
valid_sources[0x36]	538	1			T150	1		T23	8		T24	8
valid_sources[0x37]	517	1			T18	1		T150	2		T23	13
valid_sources[0x38]	504	1			T12	1		T23	13		T81	1
valid_sources[0x39]	647	1			T42	1		T23	22		T45	2
valid_sources[0x3a]	773	1			T13	6		T150	3		T23	22
valid_sources[0x3b]	762	1			T9	1		T23	6		T45	1
valid_sources[0x3c]	669	1			T22	2		T23	19		T24	34
valid_sources[0x3d]	570	1			T13	3		T64	3		T23	27
valid_sources[0x3e]	807	1			T23	5		T143	1		T24	28
valid_sources[0x3f]	566	1			T18	2		T23	4		T45	1
valid_sources[0x40]	641	1			T23	21		T24	8		T69	3
valid_sources[0x41]	539	1			T23	19		T45	4		T24	23
valid_sources[0x42]	573	1			T23	16		T79	1		T24	10
valid_sources[0x43]	516	1			T23	8		T24	19		T25	4
valid_sources[0x44]	908	1			T23	9		T54	1		T24	7
valid_sources[0x45]	589	1			T18	1		T23	22		T24	8
valid_sources[0x46]	775	1			T14	2		T23	7		T24	27
valid_sources[0x47]	663	1			T23	11		T24	25		T25	9
valid_sources[0x48]	925	1			T4	5		T149	1		T23	11
valid_sources[0x49]	530	1			T65	1		T23	25		T24	13
valid_sources[0x4a]	555	1			T23	14		T115	1		T24	8
valid_sources[0x4b]	480	1			T23	14		T24	7		T102	1
valid_sources[0x4c]	503	1			T23	19		T24	11		T25	6
valid_sources[0x4d]	524	1			T151	10		T23	30		T45	4
valid_sources[0x4e]	667	1			T152	2		T23	21		T24	8
valid_sources[0x4f]	603	1			T4	7		T23	6		T24	20
valid_sources[0x50]	503	1			T150	1		T23	9		T24	19
valid_sources[0x51]	819	1			T23	16		T24	7		T69	1
valid_sources[0x52]	935	1			T23	5		T143	1		T24	11
valid_sources[0x53]	873	1			T12	2		T23	1		T24	15
valid_sources[0x54]	690	1			T23	5		T24	17		T69	1
valid_sources[0x55]	496	1			T23	27		T45	2		T24	5
valid_sources[0x56]	618	1			T42	2		T23	21		T45	1
valid_sources[0x57]	527	1			T23	5		T24	2		T69	7
valid_sources[0x58]	659	1			T23	5		T77	1		T24	6
valid_sources[0x59]	762	1			T23	9		T153	2		T24	41
valid_sources[0x5a]	510	1			T23	10		T24	18		T25	8
valid_sources[0x5b]	501	1			T23	12		T24	28		T69	1
valid_sources[0x5c]	853	1			T23	34		T154	2		T24	15
valid_sources[0x5d]	500	1			T23	7		T24	11		T69	4
valid_sources[0x5e]	558	1			T18	1		T93	1		T23	5
valid_sources[0x5f]	762	1			T23	27		T45	1		T24	31
valid_sources[0x60]	567	1			T23	12		T45	4		T24	8
valid_sources[0x61]	477	1			T4	5		T22	2		T23	1
valid_sources[0x62]	589	1			T23	23		T24	29		T69	1
valid_sources[0x63]	584	1			T23	25		T79	1		T55	1
valid_sources[0x64]	630	1			T4	11		T14	1		T23	20
valid_sources[0x65]	609	1			T23	30		T143	1		T24	8
valid_sources[0x66]	557	1			T23	8		T24	23		T25	8
valid_sources[0x67]	590	1			T9	1		T150	1		T23	28
valid_sources[0x68]	547	1			T23	17		T45	1		T24	7
valid_sources[0x69]	853	1			T4	3		T63	24		T23	22
valid_sources[0x6a]	539	1			T23	10		T24	11		T25	6
valid_sources[0x6b]	474	1			T23	6		T24	13		T25	6
valid_sources[0x6c]	531	1			T23	7		T79	1		T24	18
valid_sources[0x6d]	623	1			T23	8		T24	16		T25	5
valid_sources[0x6e]	717	1			T155	2		T23	25		T24	12
valid_sources[0x6f]	675	1			T23	34		T45	7		T8	64
valid_sources[0x70]	642	1			T23	7		T45	1		T68	2
valid_sources[0x71]	598	1			T23	17		T78	1		T24	12
valid_sources[0x72]	639	1			T23	7		T24	12		T25	6
valid_sources[0x73]	845	1			T18	1		T23	18		T75	1
valid_sources[0x74]	551	1			T23	13		T24	26		T69	1
valid_sources[0x75]	474	1			T23	2		T79	2		T24	13
valid_sources[0x76]	619	1			T23	28		T45	3		T24	17
valid_sources[0x77]	682	1			T23	18		T143	1		T24	15
valid_sources[0x78]	509	1			T24	6		T25	8		T82	2
valid_sources[0x79]	879	1			T23	23		T24	15		T25	2
valid_sources[0x7a]	673	1			T42	1		T23	18		T24	9
valid_sources[0x7b]	840	1			T23	18		T143	1		T24	14
valid_sources[0x7c]	453	1			T23	6		T24	15		T25	7
valid_sources[0x7d]	562	1			T14	1		T23	12		T45	1
valid_sources[0x7e]	778	1			T23	16		T24	20		T25	3
valid_sources[0x7f]	811	1			T23	22		T143	3		T24	39
valid_sources[0x80]	490	1			T23	18		T68	1		T24	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36843

1

T4

18

T7

27

T19

9

values[0x0]

all_enables

biggest_size

50100

1

T1

1

T4

22

T5

1

values[0x1]

all_enables

biggest_size

47777

1

T4

14

T22

2

T13

1