Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13866719

1

T2

179

T3

955

T4

22128

full_word

52878177

1

T2

1680

T3

4442

T4

295659

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66744606	1			T2	1859		T3	5397		T4	317787
auto[TlIntgErrCmd]	92	1			T60	7		T61	4		T62	3
auto[TlIntgErrData]	97	1			T60	9		T61	3		T62	6
auto[TlIntgErrBoth]	101	1			T60	4		T61	3		T62	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30477214

1

T2

911

T3

2726

T4

130972

auto[1]

36267682

1

T2

948

T3

2671

T4

186815

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6625562	1			T2	97		T3	456		T4	8493
auto[TlIntgErrNone]	partial	auto[1]	7240889	1			T2	82		T3	499		T4	13635
auto[TlIntgErrNone]	full_word	auto[0]	23851510	1			T2	814		T3	2270		T4	122479
auto[TlIntgErrNone]	full_word	auto[1]	29026645	1			T2	866		T3	2172		T4	173180
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T60	6		T61	1		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T60	1		T61	2		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T137	1		T138	1		T139	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T61	1		T135	2		T140	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T60	4		T61	2		T62	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T60	4		T61	1		T62	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T60	1		T134	1		T138	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T62	1		T136	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T60	1		T130	4		T131	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T60	3		T61	3		T62	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T141	1		T142	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T131	1		T137	1		T141	2