Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	772072	1			T6	3349		T40	1230		T7	10167
auto[1]	9657502	1			T3	2721		T4	5900		T6	10250
auto[2]	623346	1			T6	2467		T40	1047		T7	9004
auto[3]	9519520	1			T3	2670		T4	5816		T6	9540

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13689686	1			T3	3639		T4	9834		T6	388
auto[1]	1906638	1			T3	798		T4	886		T6	2557
auto[2]	1937506	1			T3	771		T4	915		T6	3397
auto[3]	3038610	1			T3	183		T4	81		T6	19264

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8404891

1

T3

5383

T4

11701

T9

33

auto[1]

12167549

1

T3

8

T4

15

T6

25606

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	241206	1			T40	989		T7	8406		T19	809
auto[0]	auto[0]	auto[1]	24768	1			T40	114		T7	823		T65	1
auto[0]	auto[0]	auto[2]	24716	1			T40	116		T7	843		T65	1
auto[0]	auto[0]	auto[3]	6131	1			T40	10		T7	79		T65	1
auto[0]	auto[1]	auto[0]	3233412	1			T3	1860		T4	4939		T9	17
auto[0]	auto[1]	auto[1]	332347	1			T3	401		T4	420		T10	231
auto[0]	auto[1]	auto[2]	326609	1			T3	374		T4	497		T10	232
auto[0]	auto[1]	auto[3]	67340	1			T3	81		T4	38		T10	19
auto[0]	auto[2]	auto[0]	191034	1			T40	893		T7	7639		T76	10
auto[0]	auto[2]	auto[1]	19395	1			T40	79		T7	720		T76	41
auto[0]	auto[2]	auto[2]	24830	1			T40	66		T7	591		T65	2
auto[0]	auto[2]	auto[3]	5273	1			T40	9		T7	47		T19	36
auto[0]	auto[3]	auto[0]	3185660	1			T3	1771		T4	4882		T9	16
auto[0]	auto[3]	auto[1]	320454	1			T3	397		T4	465		T10	193
auto[0]	auto[3]	auto[2]	333411	1			T3	397		T4	417		T10	216
auto[0]	auto[3]	auto[3]	68305	1			T3	102		T4	43		T10	23
auto[1]	auto[0]	auto[0]	15980	1			T6	104		T40	1		T7	14
auto[1]	auto[0]	auto[1]	70691	1			T6	485		T7	1		T65	860
auto[1]	auto[0]	auto[2]	70570	1			T6	521		T7	1		T65	872
auto[1]	auto[0]	auto[3]	318010	1			T6	2239		T65	3847		T115	14372
auto[1]	auto[1]	auto[0]	3408267	1			T3	5		T4	5		T6	205
auto[1]	auto[1]	auto[1]	575103	1			T6	1664		T9	3692		T10	1
auto[1]	auto[1]	auto[2]	534700	1			T4	1		T6	847		T9	4130
auto[1]	auto[1]	auto[3]	1179724	1			T6	7534		T9	354		T22	636
auto[1]	auto[2]	auto[0]	11191	1			T7	6		T115	681		T116	686
auto[1]	auto[2]	auto[1]	49738	1			T7	1		T115	2958		T116	3135
auto[1]	auto[2]	auto[2]	58421	1			T6	468		T65	729		T19	1
auto[1]	auto[2]	auto[3]	263464	1			T6	1999		T65	3457		T76	1
auto[1]	auto[3]	auto[0]	3402936	1			T3	3		T4	8		T6	79
auto[1]	auto[3]	auto[1]	514142	1			T4	1		T6	408		T9	4031
auto[1]	auto[3]	auto[2]	564249	1			T6	1561		T9	3674		T22	6115
auto[1]	auto[3]	auto[3]	1130363	1			T6	7492		T9	325		T22	604