Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328847508	198554	0	0
ctrl_regwen_rd_A	328847508	3507	0	0
exec_rd_A	328847508	3480	0	0
exec_regwen_rd_A	328847508	3630	0	0
readback_rd_A	328847508	2550	0	0
readback_regwen_rd_A	328847508	2124	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328847508	198554	0	0
T23	127947	5735	0	0
T24	0	6099	0	0
T25	0	2000	0	0
T45	161681	0	0	0
T56	0	8393	0	0
T58	0	3945	0	0
T59	0	6442	0	0
T70	0	4147	0	0
T71	0	7965	0	0
T72	0	2006	0	0
T73	0	4649	0	0
T74	765712	0	0	0
T75	1809	0	0	0
T76	17394	0	0	0
T77	35747	0	0	0
T78	14338	0	0	0
T79	412487	0	0	0
T80	178585	0	0	0
T81	67297	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328847508	3507	0	0
T20	991282	0	0	0
T24	197215	379	0	0
T25	35034	0	0	0
T46	0	185	0	0
T47	0	94	0	0
T59	0	248	0	0
T69	289885	0	0	0
T70	0	325	0	0
T102	8914	0	0	0
T116	152420	0	0	0
T120	0	237	0	0
T121	0	434	0	0
T122	0	132	0	0
T123	0	97	0	0
T124	0	278	0	0
T125	74865	0	0	0
T126	23239	0	0	0
T127	11022	0	0	0
T128	1616	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328847508	3480	0	0
T20	991282	0	0	0
T24	197215	371	0	0
T25	35034	0	0	0
T46	0	147	0	0
T47	0	111	0	0
T59	0	251	0	0
T69	289885	0	0	0
T70	0	255	0	0
T102	8914	0	0	0
T116	152420	0	0	0
T120	0	231	0	0
T121	0	426	0	0
T122	0	90	0	0
T123	0	149	0	0
T124	0	282	0	0
T125	74865	0	0	0
T126	23239	0	0	0
T127	11022	0	0	0
T128	1616	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328847508	3630	0	0
T20	991282	0	0	0
T24	197215	400	0	0
T25	35034	0	0	0
T46	0	240	0	0
T47	0	107	0	0
T59	0	226	0	0
T69	289885	0	0	0
T70	0	291	0	0
T102	8914	0	0	0
T116	152420	0	0	0
T120	0	396	0	0
T121	0	422	0	0
T122	0	134	0	0
T123	0	151	0	0
T124	0	303	0	0
T125	74865	0	0	0
T126	23239	0	0	0
T127	11022	0	0	0
T128	1616	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328847508	2550	0	0
T20	991282	0	0	0
T24	197215	336	0	0
T25	35034	0	0	0
T46	0	216	0	0
T47	0	67	0	0
T59	0	325	0	0
T69	289885	0	0	0
T70	0	247	0	0
T102	8914	0	0	0
T116	152420	0	0	0
T120	0	390	0	0
T121	0	340	0	0
T122	0	84	0	0
T123	0	79	0	0
T124	0	220	0	0
T125	74865	0	0	0
T126	23239	0	0	0
T127	11022	0	0	0
T128	1616	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328847508	2124	0	0
T20	991282	0	0	0
T24	197215	304	0	0
T25	35034	0	0	0
T46	0	201	0	0
T47	0	35	0	0
T59	0	218	0	0
T69	289885	0	0	0
T70	0	234	0	0
T102	8914	0	0	0
T116	152420	0	0	0
T120	0	242	0	0
T121	0	234	0	0
T122	0	68	0	0
T123	0	134	0	0
T124	0	229	0	0
T125	74865	0	0	0
T126	23239	0	0	0
T127	11022	0	0	0
T128	1616	0	0	0