Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14821551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59225965

1

T1

37900

T3

176138

T4

470657

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36926559	1			T1	104098		T3	96497		T4	257205
values[0x0]	17077377	1			T1	35484		T3	46574		T4	124232
values[0x1]	20043580	1			T1	68950		T3	50322		T4	133582

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7386696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66660820

1

T1

123390

T3

184889

T4

493040

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	292346	1			T1	869		T3	721		T4	882
valid_sources[0x01]	258487	1			T1	774		T3	832		T4	889
valid_sources[0x02]	295607	1			T1	836		T3	752		T4	953
valid_sources[0x03]	264836	1			T1	853		T3	850		T4	904
valid_sources[0x04]	278850	1			T1	817		T3	713		T4	874
valid_sources[0x05]	281122	1			T1	856		T3	773		T4	827
valid_sources[0x06]	269710	1			T1	884		T3	729		T4	888
valid_sources[0x07]	269064	1			T1	819		T3	711		T4	814
valid_sources[0x08]	262072	1			T1	727		T3	805		T4	856
valid_sources[0x09]	254448	1			T1	800		T3	744		T4	1183
valid_sources[0x0a]	265978	1			T1	855		T3	766		T4	874
valid_sources[0x0b]	291123	1			T1	808		T3	725		T4	885
valid_sources[0x0c]	287122	1			T1	773		T3	754		T4	864
valid_sources[0x0d]	296246	1			T1	803		T3	737		T4	979
valid_sources[0x0e]	273378	1			T1	841		T3	713		T4	838
valid_sources[0x0f]	257024	1			T1	834		T3	699		T4	1016
valid_sources[0x10]	348197	1			T1	843		T3	707		T4	808
valid_sources[0x11]	287398	1			T1	819		T3	721		T4	907
valid_sources[0x12]	254126	1			T1	780		T3	730		T4	898
valid_sources[0x13]	263049	1			T1	759		T3	793		T4	861
valid_sources[0x14]	272534	1			T1	763		T3	811		T4	1024
valid_sources[0x15]	290510	1			T1	857		T3	690		T4	880
valid_sources[0x16]	313040	1			T1	851		T3	770		T4	836
valid_sources[0x17]	271195	1			T1	789		T3	690		T4	958
valid_sources[0x18]	273454	1			T1	796		T3	681		T4	1005
valid_sources[0x19]	323074	1			T1	814		T3	707		T4	956
valid_sources[0x1a]	292662	1			T1	872		T3	681		T4	785
valid_sources[0x1b]	262449	1			T1	920		T3	794		T4	780
valid_sources[0x1c]	266890	1			T1	779		T3	746		T4	862
valid_sources[0x1d]	315739	1			T1	833		T3	764		T4	891
valid_sources[0x1e]	283478	1			T1	837		T3	743		T4	936
valid_sources[0x1f]	309204	1			T1	836		T3	767		T4	985
valid_sources[0x20]	332325	1			T1	806		T3	738		T4	950
valid_sources[0x21]	256976	1			T1	859		T3	689		T4	726
valid_sources[0x22]	273831	1			T1	812		T3	814		T4	835
valid_sources[0x23]	419210	1			T1	803		T3	720		T4	746
valid_sources[0x24]	302544	1			T1	815		T3	690		T4	852
valid_sources[0x25]	269142	1			T1	807		T3	803		T4	766
valid_sources[0x26]	263823	1			T1	814		T3	773		T4	769
valid_sources[0x27]	310451	1			T1	836		T3	738		T4	925
valid_sources[0x28]	312024	1			T1	788		T3	827		T4	900
valid_sources[0x29]	320357	1			T1	750		T3	830		T4	1001
valid_sources[0x2a]	267344	1			T1	867		T3	793		T4	892
valid_sources[0x2b]	295570	1			T1	822		T3	698		T4	1039
valid_sources[0x2c]	261441	1			T1	793		T3	787		T4	916
valid_sources[0x2d]	274278	1			T1	840		T3	848		T4	850
valid_sources[0x2e]	264503	1			T1	814		T3	805		T4	944
valid_sources[0x2f]	264225	1			T1	738		T3	733		T4	713
valid_sources[0x30]	286636	1			T1	771		T3	755		T4	769
valid_sources[0x31]	309100	1			T1	817		T3	909		T4	681
valid_sources[0x32]	279493	1			T1	781		T3	754		T4	7954
valid_sources[0x33]	312213	1			T1	851		T3	791		T4	831
valid_sources[0x34]	272233	1			T1	782		T3	696		T4	934
valid_sources[0x35]	251907	1			T1	849		T3	762		T4	1092
valid_sources[0x36]	280157	1			T1	799		T3	746		T4	1017
valid_sources[0x37]	285313	1			T1	814		T3	781		T4	973
valid_sources[0x38]	264726	1			T1	799		T3	825		T4	881
valid_sources[0x39]	252337	1			T1	792		T3	793		T4	802
valid_sources[0x3a]	263746	1			T1	845		T3	692		T4	960
valid_sources[0x3b]	271290	1			T1	834		T3	744		T4	841
valid_sources[0x3c]	255485	1			T1	808		T3	702		T4	935
valid_sources[0x3d]	278333	1			T1	814		T3	780		T4	815
valid_sources[0x3e]	318369	1			T1	775		T3	766		T4	808
valid_sources[0x3f]	291993	1			T1	821		T3	740		T4	861
valid_sources[0x40]	287604	1			T1	784		T3	777		T4	963
valid_sources[0x41]	328276	1			T1	827		T3	723		T4	855
valid_sources[0x42]	307616	1			T1	844		T3	805		T4	767
valid_sources[0x43]	284448	1			T1	740		T3	756		T4	896
valid_sources[0x44]	264659	1			T1	808		T3	695		T4	886
valid_sources[0x45]	268045	1			T1	825		T3	790		T4	758
valid_sources[0x46]	328657	1			T1	809		T3	759		T4	945
valid_sources[0x47]	278158	1			T1	843		T3	701		T4	750
valid_sources[0x48]	291752	1			T1	827		T3	701		T4	874
valid_sources[0x49]	349684	1			T1	813		T3	671		T4	951
valid_sources[0x4a]	263272	1			T1	803		T3	745		T4	821
valid_sources[0x4b]	264591	1			T1	804		T3	702		T4	904
valid_sources[0x4c]	252752	1			T1	843		T3	772		T4	914
valid_sources[0x4d]	322692	1			T1	811		T3	743		T4	933
valid_sources[0x4e]	264164	1			T1	745		T3	714		T4	896
valid_sources[0x4f]	295230	1			T1	756		T3	733		T4	1048
valid_sources[0x50]	286804	1			T1	761		T3	768		T4	1030
valid_sources[0x51]	302622	1			T1	771		T3	819		T4	779
valid_sources[0x52]	349652	1			T1	819		T3	734		T4	1000
valid_sources[0x53]	252945	1			T1	803		T3	728		T4	867
valid_sources[0x54]	322875	1			T1	857		T3	753		T4	939
valid_sources[0x55]	258222	1			T1	825		T3	685		T4	1025
valid_sources[0x56]	280947	1			T1	845		T3	679		T4	846
valid_sources[0x57]	329776	1			T1	738		T3	697		T4	1106
valid_sources[0x58]	312348	1			T1	846		T3	739		T4	878
valid_sources[0x59]	301215	1			T1	795		T3	753		T4	970
valid_sources[0x5a]	254636	1			T1	796		T3	764		T4	979
valid_sources[0x5b]	279571	1			T1	775		T3	812		T4	912
valid_sources[0x5c]	321925	1			T1	880		T3	785		T4	968
valid_sources[0x5d]	263052	1			T1	809		T3	779		T4	1033
valid_sources[0x5e]	263553	1			T1	777		T3	685		T4	805
valid_sources[0x5f]	315917	1			T1	822		T3	800		T4	779
valid_sources[0x60]	267038	1			T1	814		T3	738		T4	943
valid_sources[0x61]	260145	1			T1	855		T3	847		T4	8112
valid_sources[0x62]	281168	1			T1	817		T3	646		T4	828
valid_sources[0x63]	281805	1			T1	825		T3	815		T4	887
valid_sources[0x64]	273230	1			T1	813		T3	812		T4	870
valid_sources[0x65]	278465	1			T1	844		T3	773		T4	20681
valid_sources[0x66]	255467	1			T1	822		T3	791		T4	804
valid_sources[0x67]	319820	1			T1	773		T3	791		T4	852
valid_sources[0x68]	285421	1			T1	843		T3	790		T4	1104
valid_sources[0x69]	278508	1			T1	807		T3	702		T4	13297
valid_sources[0x6a]	343416	1			T1	839		T3	728		T4	869
valid_sources[0x6b]	288583	1			T1	876		T3	771		T4	904
valid_sources[0x6c]	272092	1			T1	695		T3	755		T4	972
valid_sources[0x6d]	306302	1			T1	786		T3	730		T4	959
valid_sources[0x6e]	291277	1			T1	796		T3	773		T4	17415
valid_sources[0x6f]	329517	1			T1	807		T3	776		T4	861
valid_sources[0x70]	296414	1			T1	788		T3	787		T4	861
valid_sources[0x71]	306336	1			T1	796		T3	755		T4	1015
valid_sources[0x72]	296540	1			T1	814		T3	759		T4	925
valid_sources[0x73]	257411	1			T1	798		T3	715		T4	707
valid_sources[0x74]	334853	1			T1	828		T3	758		T4	1061
valid_sources[0x75]	273058	1			T1	841		T3	839		T4	807
valid_sources[0x76]	250269	1			T1	813		T3	738		T4	952
valid_sources[0x77]	285159	1			T1	871		T3	783		T4	10128
valid_sources[0x78]	280853	1			T1	803		T3	789		T4	788
valid_sources[0x79]	257669	1			T1	829		T3	757		T4	841
valid_sources[0x7a]	273708	1			T1	813		T3	753		T4	965
valid_sources[0x7b]	286153	1			T1	851		T3	779		T4	901
valid_sources[0x7c]	266986	1			T1	811		T3	771		T4	942
valid_sources[0x7d]	272632	1			T1	768		T3	738		T4	835
valid_sources[0x7e]	305798	1			T1	769		T3	808		T4	11079
valid_sources[0x7f]	283082	1			T1	782		T3	792		T4	982
valid_sources[0x80]	361397	1			T1	762		T3	713		T4	790

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29520777

1

T1

18956

T3

87863

T4

235076

values[0x0]

all_enables

biggest_size

14853340

1

T1

9618

T3

43935

T4

117584

values[0x1]

all_enables

biggest_size

14851848

1

T1

9326

T3

44340

T4

117997

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117587

1

T2

5

T3

11

T4

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43715	1			T4	14		T22	711		T17	13
values[0x0]	51781	1			T1	4		T2	10		T3	18
values[0x1]	55275	1			T1	2		T2	7		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

125580

1

T2

5

T3

14

T4

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	782	1			T23	6		T24	13		T53	2
valid_sources[0x01]	619	1			T14	3		T22	55		T23	14
valid_sources[0x02]	758	1			T23	17		T24	19		T146	1
valid_sources[0x03]	559	1			T13	7		T39	2		T23	21
valid_sources[0x04]	491	1			T23	4		T5	1		T24	12
valid_sources[0x05]	705	1			T23	7		T24	9		T53	7
valid_sources[0x06]	529	1			T23	21		T24	6		T101	4
valid_sources[0x07]	465	1			T23	17		T5	1		T24	14
valid_sources[0x08]	622	1			T23	26		T24	5		T19	3
valid_sources[0x09]	483	1			T23	11		T24	24		T147	1
valid_sources[0x0a]	422	1			T23	11		T24	3		T41	1
valid_sources[0x0b]	689	1			T23	25		T24	19		T53	2
valid_sources[0x0c]	677	1			T23	5		T24	28		T53	2
valid_sources[0x0d]	613	1			T23	21		T24	14		T53	3
valid_sources[0x0e]	452	1			T23	20		T24	14		T53	6
valid_sources[0x0f]	1502	1			T22	164		T23	6		T24	21
valid_sources[0x10]	594	1			T23	3		T24	13		T53	1
valid_sources[0x11]	753	1			T23	6		T24	21		T148	15
valid_sources[0x12]	515	1			T23	15		T24	19		T53	5
valid_sources[0x13]	488	1			T23	18		T24	46		T53	2
valid_sources[0x14]	815	1			T22	3		T23	14		T31	1
valid_sources[0x15]	708	1			T23	15		T24	17		T53	3
valid_sources[0x16]	645	1			T23	15		T24	18		T53	3
valid_sources[0x17]	467	1			T8	12		T23	7		T24	20
valid_sources[0x18]	435	1			T2	2		T23	6		T32	4
valid_sources[0x19]	518	1			T23	22		T24	18		T68	10
valid_sources[0x1a]	616	1			T23	6		T5	1		T24	11
valid_sources[0x1b]	466	1			T23	17		T24	20		T102	1
valid_sources[0x1c]	568	1			T23	7		T24	13		T53	3
valid_sources[0x1d]	571	1			T3	3		T59	2		T23	24
valid_sources[0x1e]	441	1			T23	18		T24	8		T41	1
valid_sources[0x1f]	403	1			T23	14		T5	1		T24	7
valid_sources[0x20]	566	1			T23	15		T24	11		T53	4
valid_sources[0x21]	476	1			T37	2		T23	21		T24	17
valid_sources[0x22]	568	1			T39	1		T23	13		T24	21
valid_sources[0x23]	597	1			T23	21		T24	17		T53	6
valid_sources[0x24]	555	1			T2	2		T23	20		T24	5
valid_sources[0x25]	690	1			T22	117		T23	5		T24	10
valid_sources[0x26]	566	1			T23	13		T24	19		T102	1
valid_sources[0x27]	525	1			T2	2		T23	7		T24	14
valid_sources[0x28]	551	1			T23	8		T24	18		T104	1
valid_sources[0x29]	568	1			T23	20		T24	6		T149	1
valid_sources[0x2a]	535	1			T23	13		T5	1		T24	12
valid_sources[0x2b]	556	1			T23	19		T24	29		T53	6
valid_sources[0x2c]	533	1			T23	26		T24	20		T53	4
valid_sources[0x2d]	536	1			T23	11		T24	3		T53	4
valid_sources[0x2e]	634	1			T14	2		T39	1		T23	13
valid_sources[0x2f]	551	1			T23	14		T24	16		T53	3
valid_sources[0x30]	654	1			T23	5		T24	11		T53	2
valid_sources[0x31]	831	1			T22	179		T23	17		T24	17
valid_sources[0x32]	399	1			T23	11		T24	18		T53	4
valid_sources[0x33]	643	1			T17	61		T23	28		T24	25
valid_sources[0x34]	603	1			T23	10		T5	1		T24	10
valid_sources[0x35]	440	1			T23	12		T24	10		T34	1
valid_sources[0x36]	827	1			T23	15		T24	8		T149	1
valid_sources[0x37]	671	1			T23	8		T24	14		T53	3
valid_sources[0x38]	440	1			T11	2		T23	6		T5	1
valid_sources[0x39]	600	1			T23	19		T24	24		T53	6
valid_sources[0x3a]	460	1			T23	23		T24	13		T53	3
valid_sources[0x3b]	692	1			T2	2		T23	11		T24	27
valid_sources[0x3c]	861	1			T23	14		T24	26		T69	83
valid_sources[0x3d]	544	1			T23	17		T24	27		T53	3
valid_sources[0x3e]	454	1			T22	5		T39	1		T23	24
valid_sources[0x3f]	750	1			T22	119		T23	32		T24	29
valid_sources[0x40]	643	1			T23	10		T24	19		T53	2
valid_sources[0x41]	530	1			T39	3		T23	9		T24	11
valid_sources[0x42]	774	1			T23	2		T24	13		T147	1
valid_sources[0x43]	451	1			T23	29		T24	7		T149	2
valid_sources[0x44]	407	1			T23	9		T24	24		T19	1
valid_sources[0x45]	694	1			T23	5		T24	17		T53	4
valid_sources[0x46]	503	1			T23	8		T24	37		T150	1
valid_sources[0x47]	512	1			T14	1		T23	20		T24	27
valid_sources[0x48]	548	1			T23	5		T24	17		T147	1
valid_sources[0x49]	662	1			T23	19		T24	17		T53	2
valid_sources[0x4a]	516	1			T2	1		T3	4		T23	26
valid_sources[0x4b]	644	1			T23	13		T24	11		T151	4
valid_sources[0x4c]	542	1			T23	12		T24	14		T53	5
valid_sources[0x4d]	602	1			T22	3		T23	25		T24	31
valid_sources[0x4e]	488	1			T23	20		T24	20		T41	1
valid_sources[0x4f]	533	1			T23	12		T24	11		T53	14
valid_sources[0x50]	459	1			T23	25		T24	17		T53	7
valid_sources[0x51]	581	1			T51	2		T23	10		T24	7
valid_sources[0x52]	525	1			T23	17		T24	7		T53	4
valid_sources[0x53]	519	1			T23	15		T24	7		T53	8
valid_sources[0x54]	668	1			T23	12		T24	15		T53	3
valid_sources[0x55]	523	1			T23	23		T24	30		T53	2
valid_sources[0x56]	470	1			T1	6		T23	12		T24	14
valid_sources[0x57]	689	1			T22	81		T23	5		T5	1
valid_sources[0x58]	583	1			T23	21		T24	12		T19	1
valid_sources[0x59]	532	1			T23	11		T24	14		T53	2
valid_sources[0x5a]	567	1			T23	22		T24	8		T147	1
valid_sources[0x5b]	614	1			T23	10		T24	26		T35	1
valid_sources[0x5c]	496	1			T14	2		T23	21		T32	3
valid_sources[0x5d]	612	1			T23	12		T24	7		T53	4
valid_sources[0x5e]	527	1			T23	7		T5	1		T24	16
valid_sources[0x5f]	472	1			T23	23		T24	11		T19	1
valid_sources[0x60]	577	1			T14	2		T23	21		T24	14
valid_sources[0x61]	801	1			T23	23		T24	17		T152	1
valid_sources[0x62]	504	1			T3	1		T23	16		T24	13
valid_sources[0x63]	692	1			T3	4		T23	7		T24	15
valid_sources[0x64]	465	1			T23	20		T24	19		T53	2
valid_sources[0x65]	793	1			T22	1		T23	25		T24	27
valid_sources[0x66]	440	1			T23	23		T24	16		T19	2
valid_sources[0x67]	546	1			T39	1		T23	18		T24	22
valid_sources[0x68]	507	1			T23	20		T24	9		T19	5
valid_sources[0x69]	539	1			T22	3		T23	29		T24	7
valid_sources[0x6a]	556	1			T23	17		T5	1		T24	19
valid_sources[0x6b]	509	1			T23	25		T24	10		T147	1
valid_sources[0x6c]	526	1			T23	4		T24	17		T19	2
valid_sources[0x6d]	473	1			T23	26		T24	15		T19	1
valid_sources[0x6e]	606	1			T9	6		T23	9		T24	10
valid_sources[0x6f]	526	1			T23	8		T24	9		T36	2
valid_sources[0x70]	424	1			T23	14		T24	7		T53	3
valid_sources[0x71]	447	1			T23	9		T24	12		T53	1
valid_sources[0x72]	706	1			T23	7		T24	20		T53	4
valid_sources[0x73]	855	1			T23	12		T24	21		T53	2
valid_sources[0x74]	547	1			T23	5		T24	9		T19	1
valid_sources[0x75]	586	1			T23	16		T24	31		T53	2
valid_sources[0x76]	483	1			T3	4		T23	18		T24	19
valid_sources[0x77]	571	1			T23	18		T24	9		T20	5
valid_sources[0x78]	465	1			T61	9		T23	15		T24	12
valid_sources[0x79]	532	1			T23	17		T24	5		T53	3
valid_sources[0x7a]	736	1			T22	3		T23	24		T24	13
valid_sources[0x7b]	556	1			T23	19		T24	21		T53	3
valid_sources[0x7c]	563	1			T23	2		T24	9		T53	7
valid_sources[0x7d]	739	1			T23	18		T32	3		T24	24
valid_sources[0x7e]	738	1			T23	6		T24	9		T53	3
valid_sources[0x7f]	544	1			T23	6		T24	10		T53	3
valid_sources[0x80]	490	1			T23	14		T24	15		T34	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

32316

1

T4

6

T22

647

T17

5

values[0x0]

all_enables

biggest_size

43887

1

T2

1

T3

6

T4

16

values[0x1]

all_enables

biggest_size

41384

1

T2

4

T3

5

T4

4