Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14505300

1

T1

170632

T3

13813

T4

39700

full_word

54447202

1

T1

37900

T3

140874

T4

423468

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68952232	1			T1	208532		T3	154687		T4	463168
auto[TlIntgErrCmd]	88	1			T62	6		T63	5		T64	4
auto[TlIntgErrData]	93	1			T62	10		T63	4		T64	2
auto[TlIntgErrBoth]	89	1			T62	4		T63	1		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31786892

1

T1

104098

T3

57791

T4

205729

auto[1]

37165610

1

T1

104434

T3

96896

T4

257439

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6969286	1			T1	85142		T3	5192		T4	17496
auto[TlIntgErrNone]	partial	auto[1]	7535761	1			T1	85490		T3	8621		T4	22204
auto[TlIntgErrNone]	full_word	auto[0]	24817497	1			T1	18956		T3	52599		T4	188233
auto[TlIntgErrNone]	full_word	auto[1]	29629688	1			T1	18944		T3	88275		T4	235235
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T62	4		T63	1		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T62	2		T63	4		T64	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T132	1		T137	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T132	1		T138	1		T139	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T62	4		T63	1		T64	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T62	4		T63	3		T64	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T62	1		T126	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T62	1		T136	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T62	2		T64	1		T135	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T62	2		T63	1		T64	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T135	1		T132	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T129	1		-	-		-	-