Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	827744	1			T1	24106		T3	1030		T4	16907
auto[1]	10452473	1			T1	20570		T3	662		T4	3987
auto[2]	649012	1			T1	17323		T3	647		T4	15179
auto[3]	10282113	1			T1	14032		T3	398		T4	2420

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14391492	1			T1	1729		T3	2122		T4	30298
auto[1]	2118931	1			T1	10758		T3	258		T4	4073
auto[2]	2125623	1			T1	9052		T3	321		T4	3616
auto[3]	3575296	1			T1	54492		T3	36		T4	506

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8429222

1

T3

2734

T4

38438

T9

42

auto[1]

13782120

1

T1

76031

T3

3

T4

55

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	256316	1			T3	873		T4	14047		T38	4
auto[0]	auto[0]	auto[1]	26653	1			T3	89		T4	1343		T38	16
auto[0]	auto[0]	auto[2]	26555	1			T3	63		T4	1359		T38	11
auto[0]	auto[0]	auto[3]	7104	1			T3	2		T4	135		T38	86
auto[0]	auto[1]	auto[0]	3228229	1			T3	519		T4	2184		T9	4
auto[0]	auto[1]	auto[1]	332015	1			T3	84		T4	1406		T9	2
auto[0]	auto[1]	auto[2]	326101	1			T3	49		T4	241		T9	8
auto[0]	auto[1]	auto[3]	62214	1			T3	10		T4	151		T9	9
auto[0]	auto[2]	auto[0]	210281	1			T3	490		T4	12866		T42	364
auto[0]	auto[2]	auto[1]	21400	1			T3	53		T4	1205		T42	33
auto[0]	auto[2]	auto[2]	25730	1			T3	94		T4	971		T38	7
auto[0]	auto[2]	auto[3]	6105	1			T3	10		T4	112		T38	51
auto[0]	auto[3]	auto[0]	3182083	1			T3	237		T4	1153		T11	1986
auto[0]	auto[3]	auto[1]	321290	1			T3	32		T4	115		T9	4
auto[0]	auto[3]	auto[2]	333198	1			T3	115		T4	1043		T9	4
auto[0]	auto[3]	auto[3]	63948	1			T3	14		T4	107		T9	11
auto[1]	auto[0]	auto[0]	17096	1			T1	795		T3	3		T4	21
auto[1]	auto[0]	auto[1]	75569	1			T1	3502		T4	1		T35	4988
auto[1]	auto[0]	auto[2]	75674	1			T1	3592		T4	1		T35	4879
auto[1]	auto[0]	auto[3]	342777	1			T1	16217		T35	22275		T102	3317
auto[1]	auto[1]	auto[0]	3745263	1			T1	116		T4	2		T9	3836
auto[1]	auto[1]	auto[1]	668450	1			T1	3591		T4	2		T9	17425
auto[1]	auto[1]	auto[2]	630071	1			T1	583		T9	17273		T12	1
auto[1]	auto[1]	auto[3]	1460130	1			T1	16280		T4	1		T9	78487
auto[1]	auto[2]	auto[0]	13149	1			T1	749		T4	24		T33	2
auto[1]	auto[2]	auto[1]	58352	1			T1	3303		T4	1		T35	4557
auto[1]	auto[2]	auto[2]	57647	1			T1	2475		T35	3394		T102	655
auto[1]	auto[2]	auto[3]	256348	1			T1	10796		T35	15046		T102	2937
auto[1]	auto[3]	auto[0]	3739075	1			T1	69		T4	1		T9	3863
auto[1]	auto[3]	auto[1]	615202	1			T1	362		T9	17384		T17	1
auto[1]	auto[3]	auto[2]	650647	1			T1	2402		T4	1		T9	17431
auto[1]	auto[3]	auto[3]	1376670	1			T1	11199		T9	78195		T35	15236