Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	332674428	174105	0	0
ctrl_regwen_rd_A	332674428	2382	0	0
exec_rd_A	332674428	1947	0	0
exec_regwen_rd_A	332674428	2337	0	0
readback_rd_A	332674428	1507	0	0
readback_regwen_rd_A	332674428	1482	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332674428	174105	0	0
T17	219898	0	0	0
T22	145645	3876	0	0
T23	0	5940	0	0
T24	0	6235	0	0
T37	3586	0	0	0
T38	28631	0	0	0
T39	154374	0	0	0
T42	734672	0	0	0
T47	0	4127	0	0
T51	4619	0	0	0
T53	0	1832	0	0
T58	0	2200	0	0
T59	4562	0	0	0
T60	11189	0	0	0
T61	1434	0	0	0
T70	0	902	0	0
T71	0	1254	0	0
T72	0	5971	0	0
T73	0	4321	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332674428	2382	0	0
T55	17351	0	0	0
T65	0	41	0	0
T70	19408	120	0	0
T75	0	26	0	0
T91	255639	0	0	0
T92	150547	0	0	0
T111	0	94	0	0
T112	0	236	0	0
T113	0	110	0	0
T114	0	435	0	0
T115	0	176	0	0
T116	0	336	0	0
T117	0	4	0	0
T118	5574	0	0	0
T119	1133	0	0	0
T120	48484	0	0	0
T121	135006	0	0	0
T122	43028	0	0	0
T123	12070	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332674428	1947	0	0
T55	17351	0	0	0
T64	0	28	0	0
T65	0	13	0	0
T70	19408	86	0	0
T75	0	20	0	0
T91	255639	0	0	0
T92	150547	0	0	0
T111	0	37	0	0
T112	0	218	0	0
T113	0	93	0	0
T114	0	319	0	0
T115	0	129	0	0
T116	0	311	0	0
T118	5574	0	0	0
T119	1133	0	0	0
T120	48484	0	0	0
T121	135006	0	0	0
T122	43028	0	0	0
T123	12070	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332674428	2337	0	0
T55	17351	0	0	0
T65	0	30	0	0
T70	19408	128	0	0
T75	0	38	0	0
T91	255639	0	0	0
T92	150547	0	0	0
T111	0	66	0	0
T112	0	199	0	0
T113	0	118	0	0
T114	0	340	0	0
T115	0	168	0	0
T116	0	395	0	0
T117	0	5	0	0
T118	5574	0	0	0
T119	1133	0	0	0
T120	48484	0	0	0
T121	135006	0	0	0
T122	43028	0	0	0
T123	12070	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332674428	1507	0	0
T55	17351	0	0	0
T64	0	9	0	0
T70	19408	132	0	0
T91	255639	0	0	0
T92	150547	0	0	0
T111	0	67	0	0
T112	0	180	0	0
T113	0	107	0	0
T114	0	349	0	0
T115	0	180	0	0
T116	0	345	0	0
T118	5574	0	0	0
T119	1133	0	0	0
T120	48484	0	0	0
T121	135006	0	0	0
T122	43028	0	0	0
T123	12070	0	0	0
T124	0	16	0	0
T125	0	4	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332674428	1482	0	0
T55	17351	0	0	0
T70	19408	69	0	0
T91	255639	0	0	0
T92	150547	0	0	0
T111	0	60	0	0
T112	0	177	0	0
T113	0	48	0	0
T114	0	392	0	0
T115	0	191	0	0
T116	0	406	0	0
T118	5574	0	0	0
T119	1133	0	0	0
T120	48484	0	0	0
T121	135006	0	0	0
T122	43028	0	0	0
T123	12070	0	0	0
T124	0	38	0	0
T126	0	7	0	0
T127	0	37	0	0