Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13518540

1

T1

2149

T2

2242

T3

14127

full_word

54289095

1

T1

22066

T2

22234

T3

140200

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67807345	1			T1	24215		T2	24476		T3	154327
auto[TlIntgErrCmd]	106	1			T52	1		T53	3		T54	6
auto[TlIntgErrData]	95	1			T52	8		T53	3		T54	2
auto[TlIntgErrBoth]	89	1			T52	1		T53	4		T54	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31001344

1

T1

11977

T2

12253

T3

57945

auto[1]

36806291

1

T1

12238

T2

12223

T3

96382

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6445601	1			T1	1062		T2	1113		T3	5308
auto[TlIntgErrNone]	partial	auto[1]	7072673	1			T1	1087		T2	1129		T3	8819
auto[TlIntgErrNone]	full_word	auto[0]	24555628	1			T1	10915		T2	11140		T3	52637
auto[TlIntgErrNone]	full_word	auto[1]	29733443	1			T1	11151		T2	11094		T3	87563
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T53	1		T54	3		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T52	1		T53	2		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T126	1		T127	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T128	1		T120	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	31	1			T52	4		T54	1		T121	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T52	4		T53	3		T54	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T117	1		T122	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T121	1		T118	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T53	2		T54	1		T126	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T52	1		T53	2		T54	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T122	1		T124	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T118	2		T123	2		T124	1