Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	817958	1			T3	24		T13	607		T33	25891
auto[1]	10474357	1			T1	397		T2	2415		T3	506
auto[2]	672025	1			T3	41		T13	397		T33	18716
auto[3]	10331900	1			T1	415		T2	2455		T3	515

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14426079	1			T1	695		T2	4127		T3	797
auto[1]	2123337	1			T1	55		T2	341		T3	94
auto[2]	2128995	1			T1	53		T2	371		T3	184
auto[3]	3617829	1			T1	9		T2	31		T3	11

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8193942

1

T1

811

T2

4867

T3

1085

auto[1]

14102298

1

T1

1

T2

3

T3

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	250091	1			T3	18		T13	487		T21	18
auto[0]	auto[0]	auto[1]	25765	1			T3	4		T13	46		T136	222
auto[0]	auto[0]	auto[2]	26034	1			T3	2		T13	70		T21	2
auto[0]	auto[0]	auto[3]	7174	1			T13	4		T48	6		T136	16
auto[0]	auto[1]	auto[0]	3150888	1			T1	338		T2	2064		T3	398
auto[0]	auto[1]	auto[1]	322225	1			T1	26		T2	141		T3	65
auto[0]	auto[1]	auto[2]	313632	1			T1	29		T2	197		T3	39
auto[0]	auto[1]	auto[3]	49554	1			T1	3		T2	12		T3	3
auto[0]	auto[2]	auto[0]	206365	1			T13	309		T136	1565		T36	111
auto[0]	auto[2]	auto[1]	21001	1			T13	32		T136	148		T36	15
auto[0]	auto[2]	auto[2]	24516	1			T3	39		T13	47		T21	6
auto[0]	auto[2]	auto[3]	6405	1			T3	2		T13	9		T21	1
auto[0]	auto[3]	auto[0]	3107778	1			T1	356		T2	2061		T3	380
auto[0]	auto[3]	auto[1]	309393	1			T1	29		T2	199		T3	25
auto[0]	auto[3]	auto[2]	322818	1			T1	24		T2	174		T3	104
auto[0]	auto[3]	auto[3]	50303	1			T1	6		T2	19		T3	6
auto[1]	auto[0]	auto[0]	16954	1			T33	838		T90	105		T136	3
auto[1]	auto[0]	auto[1]	75440	1			T33	3836		T90	458		T93	2518
auto[1]	auto[0]	auto[2]	75576	1			T33	3868		T90	517		T93	2482
auto[1]	auto[0]	auto[3]	340924	1			T33	17349		T90	1985		T93	11119
auto[1]	auto[1]	auto[0]	3842767	1			T1	1		T2	1		T3	1
auto[1]	auto[1]	auto[1]	679577	1			T11	2		T12	7		T25	1
auto[1]	auto[1]	auto[2]	639980	1			T11	5		T12	3		T25	1
auto[1]	auto[1]	auto[3]	1475734	1			T9	1		T11	1		T32	1
auto[1]	auto[2]	auto[0]	14042	1			T33	822		T136	1		T37	1
auto[1]	auto[2]	auto[1]	62566	1			T33	3580		T93	2206		T137	5440
auto[1]	auto[2]	auto[2]	61311	1			T33	2608		T90	409		T22	1
auto[1]	auto[2]	auto[3]	275819	1			T33	11706		T90	1962		T93	9271
auto[1]	auto[3]	auto[0]	3837194	1			T2	1		T11	31		T12	38
auto[1]	auto[3]	auto[1]	627370	1			T2	1		T9	3		T11	5
auto[1]	auto[3]	auto[2]	665128	1			T9	2		T11	5		T12	4
auto[1]	auto[3]	auto[3]	1411916	1			T32	1		T33	11844		T89	379