Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	319651253	206013	0	0
ctrl_regwen_rd_A	319651253	3308	0	0
exec_rd_A	319651253	2877	0	0
exec_regwen_rd_A	319651253	3019	0	0
readback_rd_A	319651253	2119	0	0
readback_regwen_rd_A	319651253	1904	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319651253	206013	0	0
T19	174063	7637	0	0
T20	49408	0	0	0
T21	238678	7311	0	0
T27	77974	4483	0	0
T28	1727	0	0	0
T32	4749	0	0	0
T33	174939	0	0	0
T34	5380	0	0	0
T35	65445	0	0	0
T37	0	1563	0	0
T38	0	6523	0	0
T47	0	9426	0	0
T48	6219	0	0	0
T49	0	11057	0	0
T50	0	13361	0	0
T59	0	1556	0	0
T60	0	2182	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319651253	3308	0	0
T38	199267	464	0	0
T39	0	351	0	0
T40	0	100	0	0
T98	0	218	0	0
T99	0	73	0	0
T100	0	102	0	0
T101	0	100	0	0
T102	0	133	0	0
T103	0	29	0	0
T104	0	287	0	0
T105	119330	0	0	0
T106	11771	0	0	0
T107	6544	0	0	0
T108	66666	0	0	0
T109	305370	0	0	0
T110	3510	0	0	0
T111	6861	0	0	0
T112	112410	0	0	0
T113	189408	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319651253	2877	0	0
T38	199267	306	0	0
T39	0	283	0	0
T40	0	78	0	0
T98	0	160	0	0
T99	0	86	0	0
T100	0	160	0	0
T101	0	36	0	0
T102	0	151	0	0
T103	0	25	0	0
T104	0	241	0	0
T105	119330	0	0	0
T106	11771	0	0	0
T107	6544	0	0	0
T108	66666	0	0	0
T109	305370	0	0	0
T110	3510	0	0	0
T111	6861	0	0	0
T112	112410	0	0	0
T113	189408	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319651253	3019	0	0
T38	199267	348	0	0
T39	0	299	0	0
T40	0	105	0	0
T98	0	144	0	0
T99	0	116	0	0
T100	0	187	0	0
T101	0	55	0	0
T102	0	109	0	0
T103	0	44	0	0
T104	0	279	0	0
T105	119330	0	0	0
T106	11771	0	0	0
T107	6544	0	0	0
T108	66666	0	0	0
T109	305370	0	0	0
T110	3510	0	0	0
T111	6861	0	0	0
T112	112410	0	0	0
T113	189408	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319651253	2119	0	0
T38	199267	499	0	0
T39	0	203	0	0
T40	0	86	0	0
T98	0	136	0	0
T99	0	64	0	0
T100	0	146	0	0
T101	0	30	0	0
T102	0	119	0	0
T103	0	42	0	0
T104	0	225	0	0
T105	119330	0	0	0
T106	11771	0	0	0
T107	6544	0	0	0
T108	66666	0	0	0
T109	305370	0	0	0
T110	3510	0	0	0
T111	6861	0	0	0
T112	112410	0	0	0
T113	189408	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319651253	1904	0	0
T38	199267	306	0	0
T39	0	171	0	0
T40	0	74	0	0
T98	0	139	0	0
T99	0	83	0	0
T100	0	120	0	0
T101	0	59	0	0
T102	0	86	0	0
T103	0	35	0	0
T104	0	273	0	0
T105	119330	0	0	0
T106	11771	0	0	0
T107	6544	0	0	0
T108	66666	0	0	0
T109	305370	0	0	0
T110	3510	0	0	0
T111	6861	0	0	0
T112	112410	0	0	0
T113	189408	0	0	0