Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14053522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59233811

1

T1

6890

T3

111

T4

91552

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36547131	1			T1	3498		T3	896		T4	50372
values[0x0]	16964602	1			T1	1716		T3	357		T4	24405
values[0x1]	19775600	1			T1	1676		T3	785		T4	25853

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7007364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66279969

1

T1

6890

T3

949

T4

96090

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	269564	1			T1	32		T3	3		T4	422
valid_sources[0x01]	252230	1			T1	21		T3	2		T4	419
valid_sources[0x02]	286593	1			T1	40		T3	9		T4	410
valid_sources[0x03]	300690	1			T1	30		T3	7		T4	372
valid_sources[0x04]	285605	1			T1	13		T3	11		T4	427
valid_sources[0x05]	283586	1			T1	59		T3	6		T4	367
valid_sources[0x06]	284516	1			T1	38		T3	15		T4	385
valid_sources[0x07]	297595	1			T1	14		T3	7		T4	388
valid_sources[0x08]	258852	1			T1	30		T3	1		T4	391
valid_sources[0x09]	252381	1			T1	15		T3	12		T4	395
valid_sources[0x0a]	249621	1			T1	7		T3	1		T4	376
valid_sources[0x0b]	270294	1			T1	17		T3	3		T4	388
valid_sources[0x0c]	381214	1			T1	36		T3	13		T4	397
valid_sources[0x0d]	247892	1			T1	30		T3	1		T4	371
valid_sources[0x0e]	254611	1			T1	28		T3	4		T4	415
valid_sources[0x0f]	260271	1			T1	23		T3	5		T4	428
valid_sources[0x10]	266104	1			T1	18		T4	358		T5	1812
valid_sources[0x11]	285266	1			T1	28		T3	19		T4	386
valid_sources[0x12]	323065	1			T1	25		T3	12		T4	379
valid_sources[0x13]	269785	1			T1	34		T4	377		T5	1985
valid_sources[0x14]	276741	1			T1	30		T3	10		T4	384
valid_sources[0x15]	250630	1			T1	23		T3	6		T4	414
valid_sources[0x16]	287977	1			T1	21		T3	3		T4	350
valid_sources[0x17]	284372	1			T1	15		T3	8		T4	389
valid_sources[0x18]	252814	1			T1	24		T3	5		T4	355
valid_sources[0x19]	294953	1			T1	29		T3	27		T4	387
valid_sources[0x1a]	265736	1			T1	19		T3	2		T4	391
valid_sources[0x1b]	303026	1			T1	28		T3	17		T4	375
valid_sources[0x1c]	268593	1			T1	14		T3	6		T4	407
valid_sources[0x1d]	315009	1			T1	15		T3	6		T4	395
valid_sources[0x1e]	271850	1			T1	23		T3	27		T4	397
valid_sources[0x1f]	294344	1			T1	30		T3	4		T4	383
valid_sources[0x20]	258015	1			T1	16		T4	356		T5	1840
valid_sources[0x21]	243882	1			T1	38		T4	390		T5	1861
valid_sources[0x22]	253407	1			T1	17		T3	5		T4	393
valid_sources[0x23]	281428	1			T1	19		T3	6		T4	414
valid_sources[0x24]	256395	1			T1	25		T3	12		T4	394
valid_sources[0x25]	258378	1			T1	25		T3	17		T4	402
valid_sources[0x26]	267974	1			T1	40		T3	6		T4	415
valid_sources[0x27]	275971	1			T1	34		T3	25		T4	370
valid_sources[0x28]	287391	1			T1	28		T4	388		T5	1966
valid_sources[0x29]	391179	1			T1	19		T3	28		T4	391
valid_sources[0x2a]	264670	1			T1	27		T3	2		T4	378
valid_sources[0x2b]	298983	1			T1	17		T3	11		T4	351
valid_sources[0x2c]	311037	1			T1	22		T3	21		T4	354
valid_sources[0x2d]	258511	1			T1	22		T3	7		T4	386
valid_sources[0x2e]	337176	1			T1	19		T3	6		T4	403
valid_sources[0x2f]	266074	1			T1	28		T3	4		T4	376
valid_sources[0x30]	281806	1			T1	22		T3	1		T4	416
valid_sources[0x31]	259260	1			T1	7		T3	8		T4	371
valid_sources[0x32]	267578	1			T1	21		T3	11		T4	428
valid_sources[0x33]	285806	1			T1	24		T3	6		T4	407
valid_sources[0x34]	317270	1			T1	32		T3	4		T4	396
valid_sources[0x35]	238703	1			T1	36		T3	6		T4	395
valid_sources[0x36]	274394	1			T1	13		T3	2		T4	404
valid_sources[0x37]	302470	1			T1	12		T3	11		T4	361
valid_sources[0x38]	251881	1			T1	31		T3	9		T4	390
valid_sources[0x39]	291453	1			T1	20		T3	1		T4	352
valid_sources[0x3a]	255701	1			T1	43		T4	409		T5	2012
valid_sources[0x3b]	266409	1			T1	14		T3	4		T4	367
valid_sources[0x3c]	281266	1			T1	40		T3	11		T4	444
valid_sources[0x3d]	259042	1			T1	21		T3	4		T4	359
valid_sources[0x3e]	316435	1			T1	39		T3	20		T4	366
valid_sources[0x3f]	315764	1			T1	17		T3	9		T4	407
valid_sources[0x40]	295195	1			T1	39		T3	10		T4	398
valid_sources[0x41]	266329	1			T1	40		T3	7		T4	421
valid_sources[0x42]	268543	1			T1	22		T3	5		T4	356
valid_sources[0x43]	357317	1			T1	28		T3	7		T4	396
valid_sources[0x44]	284750	1			T1	45		T3	3		T4	407
valid_sources[0x45]	307789	1			T1	27		T3	18		T4	350
valid_sources[0x46]	265599	1			T1	26		T3	1		T4	407
valid_sources[0x47]	256756	1			T1	19		T3	2		T4	412
valid_sources[0x48]	301326	1			T1	40		T3	11		T4	389
valid_sources[0x49]	350214	1			T1	20		T3	1		T4	404
valid_sources[0x4a]	253175	1			T1	27		T3	11		T4	403
valid_sources[0x4b]	305006	1			T1	32		T3	4		T4	393
valid_sources[0x4c]	250011	1			T1	15		T3	22		T4	400
valid_sources[0x4d]	277057	1			T1	20		T3	10		T4	402
valid_sources[0x4e]	277436	1			T1	22		T3	5		T4	388
valid_sources[0x4f]	311341	1			T1	37		T3	6		T4	423
valid_sources[0x50]	276090	1			T1	56		T3	1		T4	373
valid_sources[0x51]	269907	1			T1	21		T3	13		T4	403
valid_sources[0x52]	264712	1			T1	40		T3	4		T4	404
valid_sources[0x53]	263179	1			T1	45		T3	4		T4	377
valid_sources[0x54]	259461	1			T1	26		T3	5		T4	385
valid_sources[0x55]	258116	1			T1	38		T3	12		T4	398
valid_sources[0x56]	391479	1			T1	19		T3	7		T4	386
valid_sources[0x57]	249541	1			T1	26		T3	7		T4	370
valid_sources[0x58]	251440	1			T1	18		T3	4		T4	408
valid_sources[0x59]	325020	1			T1	42		T4	347		T5	1895
valid_sources[0x5a]	289144	1			T1	33		T3	17		T4	375
valid_sources[0x5b]	245326	1			T1	22		T3	5		T4	400
valid_sources[0x5c]	263503	1			T1	49		T3	13		T4	404
valid_sources[0x5d]	286794	1			T1	17		T3	4		T4	428
valid_sources[0x5e]	331480	1			T1	19		T3	6		T4	416
valid_sources[0x5f]	260037	1			T1	32		T3	9		T4	429
valid_sources[0x60]	336784	1			T1	28		T3	9		T4	397
valid_sources[0x61]	345625	1			T1	30		T3	4		T4	401
valid_sources[0x62]	384482	1			T1	32		T3	9		T4	382
valid_sources[0x63]	314029	1			T1	30		T3	14		T4	370
valid_sources[0x64]	369287	1			T1	36		T3	10		T4	394
valid_sources[0x65]	264622	1			T1	36		T3	23		T4	424
valid_sources[0x66]	322851	1			T1	30		T3	11		T4	397
valid_sources[0x67]	293219	1			T1	30		T3	2		T4	392
valid_sources[0x68]	281382	1			T1	17		T4	382		T5	1937
valid_sources[0x69]	274867	1			T1	30		T3	10		T4	430
valid_sources[0x6a]	254657	1			T1	46		T3	6		T4	387
valid_sources[0x6b]	363088	1			T1	13		T3	24		T4	411
valid_sources[0x6c]	284205	1			T1	39		T3	9		T4	371
valid_sources[0x6d]	276396	1			T1	32		T3	11		T4	377
valid_sources[0x6e]	331831	1			T1	43		T3	9		T4	425
valid_sources[0x6f]	279983	1			T1	33		T3	3		T4	395
valid_sources[0x70]	250122	1			T1	31		T3	12		T4	394
valid_sources[0x71]	288847	1			T1	36		T3	7		T4	363
valid_sources[0x72]	248143	1			T1	30		T3	6		T4	399
valid_sources[0x73]	269151	1			T1	59		T3	6		T4	395
valid_sources[0x74]	274353	1			T1	46		T3	15		T4	392
valid_sources[0x75]	253306	1			T1	20		T3	5		T4	391
valid_sources[0x76]	254451	1			T1	12		T3	27		T4	418
valid_sources[0x77]	273006	1			T1	17		T4	359		T5	1709
valid_sources[0x78]	262883	1			T1	40		T3	5		T4	373
valid_sources[0x79]	244720	1			T1	15		T4	413		T5	1990
valid_sources[0x7a]	323942	1			T1	20		T4	394		T5	1963
valid_sources[0x7b]	267760	1			T1	29		T3	5		T4	416
valid_sources[0x7c]	297252	1			T1	43		T3	1		T4	403
valid_sources[0x7d]	241394	1			T1	35		T3	8		T4	369
valid_sources[0x7e]	285503	1			T1	25		T3	11		T4	408
valid_sources[0x7f]	258155	1			T1	28		T3	14		T4	391
valid_sources[0x80]	328725	1			T1	17		T4	437		T5	1954

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29526875

1

T1

3498

T3

7

T4

45849

values[0x0]

all_enables

biggest_size

14854021

1

T1

1716

T3

54

T4

22995

values[0x1]

all_enables

biggest_size

14852915

1

T1

1676

T3

50

T4

22708

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37128	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122423

1

T2

3

T3

2

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47394	1			T5	19		T6	29		T7	54
values[0x0]	54069	1			T1	1		T2	9		T3	1
values[0x1]	58088	1			T1	1		T2	7		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28486	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

131065

1

T2

5

T3

2

T9

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	719	1			T5	3		T21	7		T42	2
valid_sources[0x01]	1126	1			T7	9		T21	18		T42	1
valid_sources[0x02]	491	1			T10	1		T71	2		T21	9
valid_sources[0x03]	752	1			T21	6		T22	9		T23	14
valid_sources[0x04]	691	1			T5	2		T21	6		T41	1
valid_sources[0x05]	545	1			T21	1		T22	9		T137	1
valid_sources[0x06]	633	1			T21	6		T22	6		T23	18
valid_sources[0x07]	661	1			T5	1		T21	17		T22	11
valid_sources[0x08]	451	1			T7	2		T21	18		T22	4
valid_sources[0x09]	362	1			T10	1		T7	2		T40	1
valid_sources[0x0a]	432	1			T10	1		T21	21		T22	8
valid_sources[0x0b]	460	1			T7	6		T21	17		T22	6
valid_sources[0x0c]	406	1			T7	1		T21	1		T42	1
valid_sources[0x0d]	389	1			T21	6		T22	6		T23	15
valid_sources[0x0e]	540	1			T21	11		T22	7		T23	13
valid_sources[0x0f]	578	1			T7	1		T21	10		T41	1
valid_sources[0x10]	784	1			T9	1		T21	3		T43	2
valid_sources[0x11]	870	1			T21	7		T42	1		T22	4
valid_sources[0x12]	512	1			T9	1		T21	12		T22	4
valid_sources[0x13]	566	1			T9	1		T21	3		T45	1
valid_sources[0x14]	540	1			T21	7		T22	3		T23	9
valid_sources[0x15]	347	1			T21	12		T42	1		T22	6
valid_sources[0x16]	509	1			T7	8		T8	7		T21	7
valid_sources[0x17]	738	1			T21	13		T22	1		T23	14
valid_sources[0x18]	451	1			T21	5		T42	1		T22	9
valid_sources[0x19]	544	1			T5	8		T21	13		T22	9
valid_sources[0x1a]	640	1			T21	17		T22	8		T23	15
valid_sources[0x1b]	593	1			T7	2		T21	3		T22	9
valid_sources[0x1c]	683	1			T21	5		T45	2		T42	2
valid_sources[0x1d]	586	1			T21	11		T45	2		T22	9
valid_sources[0x1e]	639	1			T21	4		T22	4		T23	18
valid_sources[0x1f]	522	1			T21	9		T42	1		T22	7
valid_sources[0x20]	727	1			T7	5		T21	13		T41	3
valid_sources[0x21]	636	1			T6	61		T21	18		T22	10
valid_sources[0x22]	551	1			T21	21		T45	2		T22	3
valid_sources[0x23]	933	1			T21	16		T41	1		T22	10
valid_sources[0x24]	621	1			T21	8		T22	4		T23	17
valid_sources[0x25]	739	1			T5	2		T21	13		T43	1
valid_sources[0x26]	374	1			T21	2		T43	1		T22	3
valid_sources[0x27]	746	1			T9	1		T21	21		T42	1
valid_sources[0x28]	503	1			T10	1		T21	4		T22	4
valid_sources[0x29]	628	1			T8	8		T21	6		T41	1
valid_sources[0x2a]	362	1			T21	8		T22	3		T23	11
valid_sources[0x2b]	405	1			T5	3		T21	10		T22	9
valid_sources[0x2c]	534	1			T21	10		T45	1		T22	3
valid_sources[0x2d]	478	1			T71	1		T21	5		T22	13
valid_sources[0x2e]	459	1			T21	8		T22	11		T23	15
valid_sources[0x2f]	444	1			T7	14		T21	9		T22	6
valid_sources[0x30]	813	1			T21	14		T22	8		T23	12
valid_sources[0x31]	400	1			T9	1		T21	7		T22	7
valid_sources[0x32]	453	1			T7	2		T21	6		T22	3
valid_sources[0x33]	868	1			T5	3		T21	11		T22	4
valid_sources[0x34]	724	1			T21	18		T22	7		T23	11
valid_sources[0x35]	425	1			T5	1		T21	4		T22	3
valid_sources[0x36]	480	1			T40	2		T21	22		T41	1
valid_sources[0x37]	644	1			T21	3		T22	4		T69	1
valid_sources[0x38]	707	1			T21	7		T22	7		T138	1
valid_sources[0x39]	791	1			T21	6		T22	8		T23	23
valid_sources[0x3a]	935	1			T21	8		T22	5		T23	16
valid_sources[0x3b]	854	1			T9	1		T5	3		T21	13
valid_sources[0x3c]	802	1			T21	6		T22	10		T69	1
valid_sources[0x3d]	709	1			T21	18		T42	3		T22	4
valid_sources[0x3e]	557	1			T21	8		T22	7		T23	12
valid_sources[0x3f]	570	1			T21	6		T22	8		T23	9
valid_sources[0x40]	783	1			T21	5		T45	1		T22	5
valid_sources[0x41]	626	1			T21	15		T41	1		T22	10
valid_sources[0x42]	546	1			T21	9		T41	2		T22	7
valid_sources[0x43]	690	1			T21	1		T22	5		T23	11
valid_sources[0x44]	689	1			T13	6		T21	23		T22	6
valid_sources[0x45]	579	1			T21	14		T22	9		T23	13
valid_sources[0x46]	945	1			T21	6		T22	5		T137	1
valid_sources[0x47]	378	1			T7	2		T21	4		T22	6
valid_sources[0x48]	579	1			T21	19		T22	6		T69	1
valid_sources[0x49]	595	1			T21	9		T42	1		T22	10
valid_sources[0x4a]	808	1			T21	3		T41	1		T42	1
valid_sources[0x4b]	701	1			T5	2		T10	1		T21	15
valid_sources[0x4c]	407	1			T3	1		T21	5		T43	1
valid_sources[0x4d]	615	1			T10	1		T21	7		T22	10
valid_sources[0x4e]	1201	1			T7	13		T21	13		T41	1
valid_sources[0x4f]	481	1			T5	1		T21	13		T22	2
valid_sources[0x50]	902	1			T21	9		T43	1		T22	6
valid_sources[0x51]	693	1			T21	5		T22	3		T23	10
valid_sources[0x52]	1038	1			T5	3		T21	21		T22	8
valid_sources[0x53]	590	1			T19	2		T21	13		T22	7
valid_sources[0x54]	723	1			T7	3		T21	4		T41	1
valid_sources[0x55]	449	1			T21	10		T22	5		T23	19
valid_sources[0x56]	519	1			T10	1		T7	1		T21	21
valid_sources[0x57]	673	1			T7	1		T21	16		T22	5
valid_sources[0x58]	926	1			T7	2		T21	19		T22	7
valid_sources[0x59]	673	1			T9	1		T21	7		T22	10
valid_sources[0x5a]	590	1			T5	4		T40	1		T21	13
valid_sources[0x5b]	608	1			T21	4		T22	6		T23	8
valid_sources[0x5c]	448	1			T5	2		T21	2		T22	3
valid_sources[0x5d]	382	1			T21	5		T22	7		T23	16
valid_sources[0x5e]	644	1			T21	6		T22	1		T69	1
valid_sources[0x5f]	731	1			T7	9		T21	14		T22	5
valid_sources[0x60]	550	1			T5	1		T21	12		T22	4
valid_sources[0x61]	419	1			T7	1		T21	10		T22	9
valid_sources[0x62]	667	1			T5	2		T7	1		T21	14
valid_sources[0x63]	1067	1			T21	13		T22	4		T23	12
valid_sources[0x64]	931	1			T5	2		T71	6		T21	15
valid_sources[0x65]	1067	1			T3	1		T21	9		T45	1
valid_sources[0x66]	627	1			T5	1		T71	2		T21	8
valid_sources[0x67]	524	1			T5	1		T21	8		T45	1
valid_sources[0x68]	673	1			T3	1		T21	3		T22	3
valid_sources[0x69]	586	1			T5	2		T7	4		T21	6
valid_sources[0x6a]	426	1			T39	1		T21	4		T22	4
valid_sources[0x6b]	559	1			T21	10		T22	5		T23	9
valid_sources[0x6c]	593	1			T4	13		T21	11		T22	2
valid_sources[0x6d]	740	1			T9	1		T21	15		T22	7
valid_sources[0x6e]	705	1			T9	1		T21	14		T22	1
valid_sources[0x6f]	433	1			T7	3		T21	11		T45	2
valid_sources[0x70]	364	1			T10	1		T21	13		T22	1
valid_sources[0x71]	751	1			T21	9		T22	18		T23	14
valid_sources[0x72]	685	1			T21	24		T43	1		T22	6
valid_sources[0x73]	388	1			T21	19		T22	5		T23	24
valid_sources[0x74]	500	1			T5	1		T21	5		T22	11
valid_sources[0x75]	677	1			T21	8		T22	7		T23	12
valid_sources[0x76]	904	1			T21	8		T41	1		T22	9
valid_sources[0x77]	545	1			T21	1		T41	1		T22	7
valid_sources[0x78]	954	1			T20	1		T8	3		T21	9
valid_sources[0x79]	695	1			T21	12		T22	5		T23	10
valid_sources[0x7a]	549	1			T21	6		T42	1		T22	9
valid_sources[0x7b]	773	1			T21	12		T22	8		T137	1
valid_sources[0x7c]	545	1			T21	3		T22	5		T137	2
valid_sources[0x7d]	648	1			T9	2		T11	19		T21	11
valid_sources[0x7e]	754	1			T7	3		T21	7		T22	7
valid_sources[0x7f]	879	1			T21	13		T22	4		T23	12
valid_sources[0x80]	772	1			T7	2		T21	14		T22	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33844

1

T5

9

T6

15

T7

30

values[0x0]

all_enables

biggest_size

45116

1

T2

3

T9

1

T4

6

values[0x1]

all_enables

biggest_size

43463

1

T3

2

T9

2

T4

1