Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13655375

1

T3

1927

T4

7275

T5

32385

full_word

53689903

1

T1

6890

T3

111

T4

73209

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67344938	1			T1	6890		T3	2038		T4	80484
auto[TlIntgErrCmd]	116	1			T64	7		T65	9		T66	12
auto[TlIntgErrData]	107	1			T64	5		T65	5		T66	4
auto[TlIntgErrBoth]	117	1			T64	8		T65	6		T66	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30575516

1

T1

3498

T3

896

T4

30226

auto[1]

36769762

1

T1

3392

T3

1142

T4

50258

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6506026	1			T3	889		T4	2720		T5	12087
auto[TlIntgErrNone]	partial	auto[1]	7149037	1			T3	1038		T4	4555		T5	20298
auto[TlIntgErrNone]	full_word	auto[0]	24069335	1			T1	3498		T3	7		T4	27506
auto[TlIntgErrNone]	full_word	auto[1]	29620540	1			T1	3392		T3	104		T4	45703
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T64	3		T65	5		T66	7
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T64	4		T65	4		T66	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T126	2		T127	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T122	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T64	1		T66	3		T124	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T64	4		T65	2		T66	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T65	2		T124	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T65	1		T128	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T64	2		T66	2		T124	4
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T64	4		T65	6		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T64	2		T119	2		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T129	1		T130	2		-	-