Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	693805	1			T3	47		T6	2		T8	5
auto[1]	10180764	1			T1	3497		T3	134		T4	2551
auto[2]	577871	1			T3	26		T6	1		T8	11
auto[3]	10066745	1			T1	3391		T3	187		T4	2700

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13620032	1			T1	6888		T4	4365		T5	19790
auto[1]	2085129	1			T3	5		T4	451		T5	1951
auto[2]	2103252	1			T3	23		T4	392		T5	1934
auto[3]	3710772	1			T3	366		T4	43		T5	177

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7801258

1

T1

6880

T3

394

T4

5248

auto[1]

13717927

1

T1

8

T4

3

T5

14

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	293328	1			T8	3		T40	3798		T45	6
auto[0]	auto[0]	auto[1]	30188	1			T3	1		T6	1		T8	1
auto[0]	auto[0]	auto[2]	30068	1			T6	1		T8	1		T40	335
auto[0]	auto[0]	auto[3]	8440	1			T3	46		T40	34		T45	1
auto[0]	auto[1]	auto[0]	2917978	1			T1	3494		T4	2095		T5	9811
auto[0]	auto[1]	auto[1]	308822	1			T3	1		T4	234		T5	933
auto[0]	auto[1]	auto[2]	294748	1			T3	13		T4	198		T5	1006
auto[0]	auto[1]	auto[3]	69219	1			T3	120		T4	24		T5	95
auto[0]	auto[2]	auto[0]	249252	1			T8	8		T40	3443		T41	1548
auto[0]	auto[2]	auto[1]	25670	1			T8	3		T40	379		T41	156
auto[0]	auto[2]	auto[2]	27602	1			T6	1		T40	310		T45	21
auto[0]	auto[2]	auto[3]	6773	1			T3	26		T40	38		T41	12
auto[0]	auto[3]	auto[0]	2870709	1			T1	3386		T4	2267		T5	9967
auto[0]	auto[3]	auto[1]	290661	1			T3	3		T4	217		T5	1017
auto[0]	auto[3]	auto[2]	307413	1			T3	10		T4	194		T5	927
auto[0]	auto[3]	auto[3]	70387	1			T3	174		T4	19		T5	82
auto[1]	auto[0]	auto[0]	11244	1			T40	3		T17	18		T107	479
auto[1]	auto[0]	auto[1]	49365	1			T40	1		T17	1		T107	2115
auto[1]	auto[0]	auto[2]	49249	1			T41	1		T17	1		T107	2082
auto[1]	auto[0]	auto[3]	221923	1			T107	9416		T110	14324		T112	1860
auto[1]	auto[1]	auto[0]	3637375	1			T1	3		T5	7		T12	74684
auto[1]	auto[1]	auto[1]	686606	1			T5	1		T12	6654		T13	5573
auto[1]	auto[1]	auto[2]	674582	1			T12	7573		T13	6371		T39	1
auto[1]	auto[1]	auto[3]	1591434	1			T12	711		T13	545		T39	3
auto[1]	auto[2]	auto[0]	7903	1			T40	7		T41	2		T17	14
auto[1]	auto[2]	auto[1]	34425	1			T17	2		T107	1924		T135	1
auto[1]	auto[2]	auto[2]	41104	1			T40	1		T107	1761		T110	2614
auto[1]	auto[2]	auto[3]	185142	1			T107	7948		T110	11884		T112	1680
auto[1]	auto[3]	auto[0]	3632243	1			T1	5		T4	3		T5	5
auto[1]	auto[3]	auto[1]	659392	1			T12	7585		T13	6252		T39	1
auto[1]	auto[3]	auto[2]	678486	1			T5	1		T12	6699		T13	5660
auto[1]	auto[3]	auto[3]	1557454	1			T12	671		T13	540		T57	1