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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1024
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T793 /workspace/coverage/default/49.sram_ctrl_bijection.816739740 Aug 17 05:21:55 PM PDT 24 Aug 17 05:23:02 PM PDT 24 1210800713 ps
T794 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2803933052 Aug 17 05:16:12 PM PDT 24 Aug 17 05:16:22 PM PDT 24 3090916171 ps
T795 /workspace/coverage/default/8.sram_ctrl_ram_cfg.1711531302 Aug 17 05:11:21 PM PDT 24 Aug 17 05:11:22 PM PDT 24 27878718 ps
T796 /workspace/coverage/default/48.sram_ctrl_regwen.3966907608 Aug 17 05:21:55 PM PDT 24 Aug 17 05:34:35 PM PDT 24 24212947806 ps
T797 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.790717401 Aug 17 05:17:24 PM PDT 24 Aug 17 05:21:26 PM PDT 24 3393973267 ps
T798 /workspace/coverage/default/7.sram_ctrl_max_throughput.1104912368 Aug 17 05:10:59 PM PDT 24 Aug 17 05:12:55 PM PDT 24 159977323 ps
T799 /workspace/coverage/default/4.sram_ctrl_smoke.3776755749 Aug 17 05:10:20 PM PDT 24 Aug 17 05:10:23 PM PDT 24 500545143 ps
T800 /workspace/coverage/default/26.sram_ctrl_alert_test.2029760725 Aug 17 05:16:19 PM PDT 24 Aug 17 05:16:20 PM PDT 24 15999270 ps
T801 /workspace/coverage/default/3.sram_ctrl_partial_access.433439760 Aug 17 05:10:21 PM PDT 24 Aug 17 05:11:47 PM PDT 24 1588913099 ps
T802 /workspace/coverage/default/23.sram_ctrl_bijection.3526548841 Aug 17 05:15:13 PM PDT 24 Aug 17 05:15:33 PM PDT 24 1802292514 ps
T803 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.120393694 Aug 17 05:21:55 PM PDT 24 Aug 17 05:31:23 PM PDT 24 16309331288 ps
T804 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2047617143 Aug 17 05:16:53 PM PDT 24 Aug 17 05:16:55 PM PDT 24 757849507 ps
T805 /workspace/coverage/default/10.sram_ctrl_bijection.2127057057 Aug 17 05:11:34 PM PDT 24 Aug 17 05:12:54 PM PDT 24 4640870947 ps
T806 /workspace/coverage/default/25.sram_ctrl_partial_access.4005417029 Aug 17 05:15:48 PM PDT 24 Aug 17 05:16:00 PM PDT 24 642196539 ps
T807 /workspace/coverage/default/20.sram_ctrl_max_throughput.201784612 Aug 17 05:14:25 PM PDT 24 Aug 17 05:15:02 PM PDT 24 95306367 ps
T808 /workspace/coverage/default/21.sram_ctrl_smoke.3138549892 Aug 17 05:14:32 PM PDT 24 Aug 17 05:14:45 PM PDT 24 405825465 ps
T809 /workspace/coverage/default/28.sram_ctrl_multiple_keys.1923723406 Aug 17 05:16:44 PM PDT 24 Aug 17 05:42:24 PM PDT 24 84675404956 ps
T810 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3803891938 Aug 17 05:12:14 PM PDT 24 Aug 17 05:12:22 PM PDT 24 7422682663 ps
T811 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.886655630 Aug 17 05:19:31 PM PDT 24 Aug 17 05:36:28 PM PDT 24 19450316964 ps
T812 /workspace/coverage/default/32.sram_ctrl_ram_cfg.713469892 Aug 17 05:17:58 PM PDT 24 Aug 17 05:17:59 PM PDT 24 27453531 ps
T813 /workspace/coverage/default/37.sram_ctrl_ram_cfg.1432880943 Aug 17 05:19:24 PM PDT 24 Aug 17 05:19:25 PM PDT 24 48148650 ps
T814 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.703372634 Aug 17 05:17:11 PM PDT 24 Aug 17 05:27:55 PM PDT 24 10136032672 ps
T815 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1424461299 Aug 17 05:12:54 PM PDT 24 Aug 17 05:29:49 PM PDT 24 4138577854 ps
T816 /workspace/coverage/default/19.sram_ctrl_max_throughput.2126297994 Aug 17 05:14:00 PM PDT 24 Aug 17 05:16:13 PM PDT 24 541512522 ps
T817 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2762542401 Aug 17 05:12:39 PM PDT 24 Aug 17 05:14:29 PM PDT 24 303277792 ps
T94 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2322449519 Aug 17 05:18:56 PM PDT 24 Aug 17 05:18:59 PM PDT 24 145332187 ps
T818 /workspace/coverage/default/40.sram_ctrl_bijection.1902656489 Aug 17 05:19:58 PM PDT 24 Aug 17 05:21:18 PM PDT 24 24386566435 ps
T819 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1904499101 Aug 17 05:11:01 PM PDT 24 Aug 17 05:14:38 PM PDT 24 13643525267 ps
T820 /workspace/coverage/default/8.sram_ctrl_multiple_keys.660728448 Aug 17 05:11:07 PM PDT 24 Aug 17 05:30:56 PM PDT 24 12887800451 ps
T821 /workspace/coverage/default/30.sram_ctrl_stress_all.2922776463 Aug 17 05:17:30 PM PDT 24 Aug 17 05:44:08 PM PDT 24 105368152642 ps
T822 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3500573377 Aug 17 05:10:26 PM PDT 24 Aug 17 05:24:13 PM PDT 24 14329039128 ps
T823 /workspace/coverage/default/14.sram_ctrl_stress_all.429902499 Aug 17 05:12:47 PM PDT 24 Aug 17 06:36:54 PM PDT 24 71633783910 ps
T824 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.910969470 Aug 17 05:10:12 PM PDT 24 Aug 17 05:15:56 PM PDT 24 19221257872 ps
T825 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.519622169 Aug 17 05:19:52 PM PDT 24 Aug 17 05:20:39 PM PDT 24 1660685032 ps
T826 /workspace/coverage/default/0.sram_ctrl_lc_escalation.4184112504 Aug 17 05:09:55 PM PDT 24 Aug 17 05:10:05 PM PDT 24 641713956 ps
T827 /workspace/coverage/default/31.sram_ctrl_max_throughput.3860993796 Aug 17 05:17:41 PM PDT 24 Aug 17 05:17:45 PM PDT 24 95196905 ps
T828 /workspace/coverage/default/48.sram_ctrl_bijection.3603179068 Aug 17 05:21:44 PM PDT 24 Aug 17 05:22:38 PM PDT 24 1789690013 ps
T829 /workspace/coverage/default/0.sram_ctrl_bijection.1967692605 Aug 17 05:09:55 PM PDT 24 Aug 17 05:11:08 PM PDT 24 6698217030 ps
T830 /workspace/coverage/default/29.sram_ctrl_bijection.2712667531 Aug 17 05:17:01 PM PDT 24 Aug 17 05:18:04 PM PDT 24 3884224219 ps
T831 /workspace/coverage/default/49.sram_ctrl_regwen.3342086417 Aug 17 05:22:04 PM PDT 24 Aug 17 05:26:25 PM PDT 24 2173481867 ps
T832 /workspace/coverage/default/2.sram_ctrl_stress_all.1099035654 Aug 17 05:10:12 PM PDT 24 Aug 17 05:53:22 PM PDT 24 47826906167 ps
T833 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3050543170 Aug 17 05:14:43 PM PDT 24 Aug 17 05:19:23 PM PDT 24 11941623758 ps
T834 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.111295315 Aug 17 05:10:42 PM PDT 24 Aug 17 05:12:50 PM PDT 24 25646954985 ps
T835 /workspace/coverage/default/35.sram_ctrl_ram_cfg.1489808016 Aug 17 05:18:46 PM PDT 24 Aug 17 05:18:47 PM PDT 24 29441303 ps
T836 /workspace/coverage/default/41.sram_ctrl_executable.3123687167 Aug 17 05:20:07 PM PDT 24 Aug 17 05:30:24 PM PDT 24 36944969778 ps
T837 /workspace/coverage/default/48.sram_ctrl_partial_access.1696413804 Aug 17 05:21:45 PM PDT 24 Aug 17 05:21:50 PM PDT 24 520689242 ps
T838 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2980451057 Aug 17 05:16:43 PM PDT 24 Aug 17 05:20:16 PM PDT 24 8590822740 ps
T839 /workspace/coverage/default/47.sram_ctrl_mem_walk.4225657392 Aug 17 05:21:36 PM PDT 24 Aug 17 05:21:42 PM PDT 24 354493096 ps
T840 /workspace/coverage/default/16.sram_ctrl_stress_all.2740103844 Aug 17 05:13:19 PM PDT 24 Aug 17 06:19:08 PM PDT 24 28281984034 ps
T841 /workspace/coverage/default/15.sram_ctrl_mem_walk.4278779628 Aug 17 05:12:56 PM PDT 24 Aug 17 05:13:01 PM PDT 24 240041571 ps
T842 /workspace/coverage/default/3.sram_ctrl_max_throughput.2153840532 Aug 17 05:10:21 PM PDT 24 Aug 17 05:10:51 PM PDT 24 93470328 ps
T843 /workspace/coverage/default/16.sram_ctrl_smoke.3546496839 Aug 17 05:13:03 PM PDT 24 Aug 17 05:13:06 PM PDT 24 620259661 ps
T844 /workspace/coverage/default/8.sram_ctrl_partial_access.1327497365 Aug 17 05:11:09 PM PDT 24 Aug 17 05:11:16 PM PDT 24 1107985010 ps
T845 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3655882041 Aug 17 05:16:27 PM PDT 24 Aug 17 05:22:48 PM PDT 24 20848194564 ps
T846 /workspace/coverage/default/36.sram_ctrl_smoke.2544834656 Aug 17 05:18:54 PM PDT 24 Aug 17 05:19:06 PM PDT 24 356933902 ps
T847 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3900725048 Aug 17 05:19:59 PM PDT 24 Aug 17 05:26:19 PM PDT 24 16499459723 ps
T848 /workspace/coverage/default/15.sram_ctrl_ram_cfg.1013517870 Aug 17 05:12:55 PM PDT 24 Aug 17 05:12:56 PM PDT 24 31412066 ps
T849 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2106376490 Aug 17 05:16:28 PM PDT 24 Aug 17 05:20:46 PM PDT 24 5096340609 ps
T850 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3546961000 Aug 17 05:10:20 PM PDT 24 Aug 17 05:14:27 PM PDT 24 10346567131 ps
T851 /workspace/coverage/default/8.sram_ctrl_bijection.952288283 Aug 17 05:11:08 PM PDT 24 Aug 17 05:11:30 PM PDT 24 1852657239 ps
T852 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.620587997 Aug 17 05:10:28 PM PDT 24 Aug 17 05:10:34 PM PDT 24 454073425 ps
T853 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1871799843 Aug 17 05:16:13 PM PDT 24 Aug 17 05:16:14 PM PDT 24 28851035 ps
T854 /workspace/coverage/default/11.sram_ctrl_stress_all.2044808141 Aug 17 05:12:07 PM PDT 24 Aug 17 05:40:37 PM PDT 24 19004165632 ps
T855 /workspace/coverage/default/43.sram_ctrl_bijection.1789804364 Aug 17 05:20:38 PM PDT 24 Aug 17 05:21:08 PM PDT 24 1827860773 ps
T856 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3341477383 Aug 17 05:15:54 PM PDT 24 Aug 17 05:21:03 PM PDT 24 1640490428 ps
T857 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2025646301 Aug 17 05:14:01 PM PDT 24 Aug 17 05:22:26 PM PDT 24 19353274936 ps
T858 /workspace/coverage/default/19.sram_ctrl_multiple_keys.1284192524 Aug 17 05:14:00 PM PDT 24 Aug 17 05:24:42 PM PDT 24 10243379463 ps
T95 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.528708348 Aug 17 05:10:05 PM PDT 24 Aug 17 05:10:08 PM PDT 24 63397076 ps
T859 /workspace/coverage/default/36.sram_ctrl_bijection.3163625072 Aug 17 05:18:54 PM PDT 24 Aug 17 05:19:52 PM PDT 24 4033857505 ps
T860 /workspace/coverage/default/11.sram_ctrl_mem_walk.669524563 Aug 17 05:12:05 PM PDT 24 Aug 17 05:12:16 PM PDT 24 1743931838 ps
T861 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1801361520 Aug 17 05:14:34 PM PDT 24 Aug 17 05:25:08 PM PDT 24 18207310651 ps
T862 /workspace/coverage/default/12.sram_ctrl_executable.3423241257 Aug 17 05:12:09 PM PDT 24 Aug 17 05:36:40 PM PDT 24 13660320472 ps
T863 /workspace/coverage/default/37.sram_ctrl_max_throughput.167314678 Aug 17 05:19:17 PM PDT 24 Aug 17 05:20:47 PM PDT 24 136607895 ps
T864 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2039771431 Aug 17 05:19:59 PM PDT 24 Aug 17 05:27:13 PM PDT 24 9606427644 ps
T865 /workspace/coverage/default/13.sram_ctrl_stress_all.4219899449 Aug 17 05:12:24 PM PDT 24 Aug 17 05:44:06 PM PDT 24 33721852239 ps
T866 /workspace/coverage/default/36.sram_ctrl_multiple_keys.153578427 Aug 17 05:18:56 PM PDT 24 Aug 17 05:28:03 PM PDT 24 99685109174 ps
T867 /workspace/coverage/default/46.sram_ctrl_max_throughput.2166647196 Aug 17 05:21:25 PM PDT 24 Aug 17 05:22:16 PM PDT 24 102761524 ps
T868 /workspace/coverage/default/16.sram_ctrl_multiple_keys.390037580 Aug 17 05:13:03 PM PDT 24 Aug 17 05:35:28 PM PDT 24 19255342698 ps
T869 /workspace/coverage/default/46.sram_ctrl_mem_walk.2444969961 Aug 17 05:21:24 PM PDT 24 Aug 17 05:21:28 PM PDT 24 86543990 ps
T870 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3979718891 Aug 17 05:15:15 PM PDT 24 Aug 17 05:18:37 PM PDT 24 1728821108 ps
T871 /workspace/coverage/default/32.sram_ctrl_regwen.332600847 Aug 17 05:17:55 PM PDT 24 Aug 17 05:37:55 PM PDT 24 8336740250 ps
T872 /workspace/coverage/default/30.sram_ctrl_alert_test.563990766 Aug 17 05:17:24 PM PDT 24 Aug 17 05:17:24 PM PDT 24 30386168 ps
T873 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1856232793 Aug 17 05:21:24 PM PDT 24 Aug 17 05:27:27 PM PDT 24 15529562564 ps
T874 /workspace/coverage/default/8.sram_ctrl_regwen.2501215699 Aug 17 05:11:20 PM PDT 24 Aug 17 05:22:30 PM PDT 24 1789085549 ps
T875 /workspace/coverage/default/34.sram_ctrl_smoke.1810357388 Aug 17 05:18:33 PM PDT 24 Aug 17 05:18:47 PM PDT 24 1851474258 ps
T876 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2041366132 Aug 17 05:14:51 PM PDT 24 Aug 17 05:14:55 PM PDT 24 406962840 ps
T877 /workspace/coverage/default/22.sram_ctrl_regwen.2214225928 Aug 17 05:15:06 PM PDT 24 Aug 17 05:18:26 PM PDT 24 902531939 ps
T878 /workspace/coverage/default/4.sram_ctrl_regwen.1417285440 Aug 17 05:10:28 PM PDT 24 Aug 17 05:26:37 PM PDT 24 12570567453 ps
T879 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.4037262451 Aug 17 05:18:39 PM PDT 24 Aug 17 05:25:57 PM PDT 24 3573639323 ps
T880 /workspace/coverage/default/4.sram_ctrl_ram_cfg.3244545957 Aug 17 05:10:27 PM PDT 24 Aug 17 05:10:28 PM PDT 24 28265623 ps
T881 /workspace/coverage/default/21.sram_ctrl_mem_walk.2640788059 Aug 17 05:14:49 PM PDT 24 Aug 17 05:14:55 PM PDT 24 339653674 ps
T882 /workspace/coverage/default/32.sram_ctrl_lc_escalation.3295233840 Aug 17 05:17:56 PM PDT 24 Aug 17 05:18:03 PM PDT 24 1755577739 ps
T883 /workspace/coverage/default/2.sram_ctrl_lc_escalation.355517580 Aug 17 05:10:11 PM PDT 24 Aug 17 05:10:16 PM PDT 24 864630629 ps
T884 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4167529471 Aug 17 05:19:25 PM PDT 24 Aug 17 05:26:09 PM PDT 24 1827794056 ps
T885 /workspace/coverage/default/20.sram_ctrl_regwen.3045731440 Aug 17 05:14:24 PM PDT 24 Aug 17 05:31:36 PM PDT 24 14562815007 ps
T886 /workspace/coverage/default/23.sram_ctrl_regwen.656581391 Aug 17 05:15:23 PM PDT 24 Aug 17 05:20:54 PM PDT 24 1090961265 ps
T887 /workspace/coverage/default/43.sram_ctrl_mem_walk.1799298994 Aug 17 05:20:48 PM PDT 24 Aug 17 05:20:59 PM PDT 24 879405384 ps
T888 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3804455725 Aug 17 05:09:57 PM PDT 24 Aug 17 05:37:36 PM PDT 24 4488828783 ps
T889 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3732580800 Aug 17 05:14:42 PM PDT 24 Aug 17 05:16:40 PM PDT 24 770165080 ps
T890 /workspace/coverage/default/27.sram_ctrl_alert_test.3608209458 Aug 17 05:16:45 PM PDT 24 Aug 17 05:16:45 PM PDT 24 21008605 ps
T891 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1524154912 Aug 17 05:12:13 PM PDT 24 Aug 17 05:12:34 PM PDT 24 157454768 ps
T892 /workspace/coverage/default/2.sram_ctrl_smoke.2029561678 Aug 17 05:10:05 PM PDT 24 Aug 17 05:10:19 PM PDT 24 2198446029 ps
T893 /workspace/coverage/default/38.sram_ctrl_executable.161483570 Aug 17 05:19:33 PM PDT 24 Aug 17 05:34:18 PM PDT 24 2745465206 ps
T894 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1511414168 Aug 17 05:15:42 PM PDT 24 Aug 17 05:30:33 PM PDT 24 25923516840 ps
T895 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.214915629 Aug 17 05:17:49 PM PDT 24 Aug 17 05:21:49 PM PDT 24 2576753892 ps
T896 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2091014594 Aug 17 05:21:03 PM PDT 24 Aug 17 05:21:06 PM PDT 24 224723771 ps
T897 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.20330310 Aug 17 05:16:12 PM PDT 24 Aug 17 05:16:46 PM PDT 24 102760883 ps
T898 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1002450552 Aug 17 05:20:37 PM PDT 24 Aug 17 05:41:19 PM PDT 24 15020633868 ps
T899 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1534516490 Aug 17 05:20:38 PM PDT 24 Aug 17 05:27:16 PM PDT 24 15484662774 ps
T900 /workspace/coverage/default/7.sram_ctrl_lc_escalation.16028491 Aug 17 05:10:59 PM PDT 24 Aug 17 05:11:00 PM PDT 24 205584936 ps
T901 /workspace/coverage/default/18.sram_ctrl_multiple_keys.3156614502 Aug 17 05:13:45 PM PDT 24 Aug 17 05:48:38 PM PDT 24 26017070219 ps
T902 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2763510058 Aug 17 05:21:46 PM PDT 24 Aug 17 05:31:58 PM PDT 24 144624249776 ps
T903 /workspace/coverage/default/34.sram_ctrl_mem_walk.1907329200 Aug 17 05:18:38 PM PDT 24 Aug 17 05:18:43 PM PDT 24 232015858 ps
T904 /workspace/coverage/default/20.sram_ctrl_partial_access.788950122 Aug 17 05:14:17 PM PDT 24 Aug 17 05:14:34 PM PDT 24 3192268469 ps
T905 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.684440027 Aug 17 05:22:08 PM PDT 24 Aug 17 05:29:36 PM PDT 24 11962633768 ps
T906 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.4003997487 Aug 17 05:13:11 PM PDT 24 Aug 17 05:19:16 PM PDT 24 43051512415 ps
T907 /workspace/coverage/default/42.sram_ctrl_stress_all.1035966711 Aug 17 05:20:30 PM PDT 24 Aug 17 06:21:54 PM PDT 24 11803169043 ps
T908 /workspace/coverage/default/31.sram_ctrl_mem_walk.1649406226 Aug 17 05:17:53 PM PDT 24 Aug 17 05:17:59 PM PDT 24 974794576 ps
T909 /workspace/coverage/default/47.sram_ctrl_ram_cfg.2047696459 Aug 17 05:21:36 PM PDT 24 Aug 17 05:21:37 PM PDT 24 36760234 ps
T910 /workspace/coverage/default/15.sram_ctrl_regwen.1168453621 Aug 17 05:12:55 PM PDT 24 Aug 17 05:27:02 PM PDT 24 34937035455 ps
T911 /workspace/coverage/default/22.sram_ctrl_executable.2518937528 Aug 17 05:15:01 PM PDT 24 Aug 17 05:24:36 PM PDT 24 8636521564 ps
T912 /workspace/coverage/default/16.sram_ctrl_executable.2939825640 Aug 17 05:13:17 PM PDT 24 Aug 17 05:15:11 PM PDT 24 10198552253 ps
T913 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1440785999 Aug 17 05:11:44 PM PDT 24 Aug 17 05:19:23 PM PDT 24 9511806580 ps
T914 /workspace/coverage/default/21.sram_ctrl_max_throughput.150725305 Aug 17 05:14:39 PM PDT 24 Aug 17 05:16:37 PM PDT 24 260089823 ps
T915 /workspace/coverage/default/47.sram_ctrl_regwen.1894046467 Aug 17 05:21:36 PM PDT 24 Aug 17 05:43:12 PM PDT 24 18993963478 ps
T916 /workspace/coverage/default/38.sram_ctrl_lc_escalation.545196994 Aug 17 05:19:33 PM PDT 24 Aug 17 05:19:40 PM PDT 24 515474739 ps
T917 /workspace/coverage/default/39.sram_ctrl_bijection.132629983 Aug 17 05:19:39 PM PDT 24 Aug 17 05:20:21 PM PDT 24 4703368924 ps
T918 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1678202983 Aug 17 05:10:05 PM PDT 24 Aug 17 05:16:19 PM PDT 24 5233615114 ps
T919 /workspace/coverage/default/38.sram_ctrl_ram_cfg.2272574495 Aug 17 05:19:32 PM PDT 24 Aug 17 05:19:33 PM PDT 24 166300869 ps
T920 /workspace/coverage/default/28.sram_ctrl_stress_all.3352958603 Aug 17 05:17:01 PM PDT 24 Aug 17 05:22:39 PM PDT 24 27374713091 ps
T921 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1301326888 Aug 17 05:15:30 PM PDT 24 Aug 17 05:21:32 PM PDT 24 13700998085 ps
T922 /workspace/coverage/default/11.sram_ctrl_partial_access.81708990 Aug 17 05:11:50 PM PDT 24 Aug 17 05:12:08 PM PDT 24 3544323017 ps
T923 /workspace/coverage/default/36.sram_ctrl_alert_test.2738997966 Aug 17 05:19:10 PM PDT 24 Aug 17 05:19:10 PM PDT 24 14151360 ps
T924 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3452543407 Aug 17 05:12:17 PM PDT 24 Aug 17 05:16:28 PM PDT 24 5155334177 ps
T925 /workspace/coverage/default/41.sram_ctrl_stress_all.571208215 Aug 17 05:20:16 PM PDT 24 Aug 17 06:05:51 PM PDT 24 17573585925 ps
T926 /workspace/coverage/default/45.sram_ctrl_bijection.2752841010 Aug 17 05:21:07 PM PDT 24 Aug 17 05:21:50 PM PDT 24 7603196730 ps
T927 /workspace/coverage/default/18.sram_ctrl_max_throughput.2431878308 Aug 17 05:13:44 PM PDT 24 Aug 17 05:16:21 PM PDT 24 638017428 ps
T928 /workspace/coverage/default/9.sram_ctrl_mem_walk.4128915270 Aug 17 05:11:27 PM PDT 24 Aug 17 05:11:37 PM PDT 24 180681563 ps
T929 /workspace/coverage/default/29.sram_ctrl_partial_access.3877485534 Aug 17 05:17:02 PM PDT 24 Aug 17 05:17:41 PM PDT 24 1584163739 ps
T930 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.521780969 Aug 17 05:19:29 PM PDT 24 Aug 17 05:25:49 PM PDT 24 32975305362 ps
T931 /workspace/coverage/default/24.sram_ctrl_smoke.1553860388 Aug 17 05:15:23 PM PDT 24 Aug 17 05:16:38 PM PDT 24 236034309 ps
T67 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3516980328 Aug 17 05:07:31 PM PDT 24 Aug 17 05:07:32 PM PDT 24 37088102 ps
T932 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4211661821 Aug 17 05:07:23 PM PDT 24 Aug 17 05:07:27 PM PDT 24 148084067 ps
T64 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.377307755 Aug 17 05:07:47 PM PDT 24 Aug 17 05:07:49 PM PDT 24 524640933 ps
T68 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2505111554 Aug 17 05:07:15 PM PDT 24 Aug 17 05:07:16 PM PDT 24 106767937 ps
T76 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4234938394 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:39 PM PDT 24 56131526 ps
T933 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2598661546 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:39 PM PDT 24 32826562 ps
T65 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.32277353 Aug 17 05:06:58 PM PDT 24 Aug 17 05:07:01 PM PDT 24 379086709 ps
T934 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2704006882 Aug 17 05:07:13 PM PDT 24 Aug 17 05:07:15 PM PDT 24 119787526 ps
T77 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3120188237 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:30 PM PDT 24 22614639 ps
T103 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3957128136 Aug 17 05:08:02 PM PDT 24 Aug 17 05:08:03 PM PDT 24 18411132 ps
T104 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4126619363 Aug 17 05:07:14 PM PDT 24 Aug 17 05:07:15 PM PDT 24 33420680 ps
T935 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4139392329 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:41 PM PDT 24 44568037 ps
T936 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4101649475 Aug 17 05:07:45 PM PDT 24 Aug 17 05:07:49 PM PDT 24 182065655 ps
T78 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3538747406 Aug 17 05:07:24 PM PDT 24 Aug 17 05:07:27 PM PDT 24 1606491416 ps
T937 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1590972686 Aug 17 05:06:49 PM PDT 24 Aug 17 05:06:51 PM PDT 24 688269477 ps
T66 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4213844372 Aug 17 05:07:57 PM PDT 24 Aug 17 05:08:00 PM PDT 24 296361273 ps
T79 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1290904882 Aug 17 05:07:47 PM PDT 24 Aug 17 05:07:50 PM PDT 24 1535569691 ps
T80 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4071414790 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:40 PM PDT 24 47273058 ps
T81 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3945182513 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:43 PM PDT 24 1842691066 ps
T938 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3638299936 Aug 17 05:07:48 PM PDT 24 Aug 17 05:07:48 PM PDT 24 51739393 ps
T124 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2888885043 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:40 PM PDT 24 140052735 ps
T82 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.317983501 Aug 17 05:07:23 PM PDT 24 Aug 17 05:07:28 PM PDT 24 5129630763 ps
T83 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3267990445 Aug 17 05:07:56 PM PDT 24 Aug 17 05:07:56 PM PDT 24 15120999 ps
T119 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1198120702 Aug 17 05:06:49 PM PDT 24 Aug 17 05:06:52 PM PDT 24 220792915 ps
T939 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1442745706 Aug 17 05:07:48 PM PDT 24 Aug 17 05:07:51 PM PDT 24 660716490 ps
T940 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1257893197 Aug 17 05:07:04 PM PDT 24 Aug 17 05:07:05 PM PDT 24 14077579 ps
T941 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3707195946 Aug 17 05:07:22 PM PDT 24 Aug 17 05:07:24 PM PDT 24 137711265 ps
T122 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1468947904 Aug 17 05:07:29 PM PDT 24 Aug 17 05:07:32 PM PDT 24 2050682358 ps
T84 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2362072542 Aug 17 05:06:49 PM PDT 24 Aug 17 05:06:50 PM PDT 24 71423436 ps
T942 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3181504029 Aug 17 05:06:58 PM PDT 24 Aug 17 05:06:59 PM PDT 24 16298434 ps
T85 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.318717046 Aug 17 05:07:37 PM PDT 24 Aug 17 05:07:38 PM PDT 24 31032998 ps
T943 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.945191560 Aug 17 05:07:31 PM PDT 24 Aug 17 05:07:33 PM PDT 24 38434971 ps
T86 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3241005863 Aug 17 05:07:24 PM PDT 24 Aug 17 05:07:27 PM PDT 24 5236920354 ps
T944 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2793143737 Aug 17 05:07:29 PM PDT 24 Aug 17 05:07:31 PM PDT 24 59311832 ps
T87 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3069264991 Aug 17 05:07:09 PM PDT 24 Aug 17 05:07:10 PM PDT 24 13657179 ps
T945 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3710009936 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:43 PM PDT 24 141974240 ps
T129 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1397653311 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:32 PM PDT 24 1265209462 ps
T946 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3103068059 Aug 17 05:07:40 PM PDT 24 Aug 17 05:07:40 PM PDT 24 62343402 ps
T947 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1025802307 Aug 17 05:07:24 PM PDT 24 Aug 17 05:07:24 PM PDT 24 23264069 ps
T128 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3840067240 Aug 17 05:07:22 PM PDT 24 Aug 17 05:07:23 PM PDT 24 203250342 ps
T88 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3502627247 Aug 17 05:07:37 PM PDT 24 Aug 17 05:07:40 PM PDT 24 1826102137 ps
T89 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4219927492 Aug 17 05:06:47 PM PDT 24 Aug 17 05:06:49 PM PDT 24 838732972 ps
T101 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.511969879 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:39 PM PDT 24 11945865 ps
T948 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2994937772 Aug 17 05:07:23 PM PDT 24 Aug 17 05:07:24 PM PDT 24 32777617 ps
T949 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2824094680 Aug 17 05:07:40 PM PDT 24 Aug 17 05:07:41 PM PDT 24 16267846 ps
T950 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2141643108 Aug 17 05:07:31 PM PDT 24 Aug 17 05:07:33 PM PDT 24 116328990 ps
T951 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3368420538 Aug 17 05:07:23 PM PDT 24 Aug 17 05:07:28 PM PDT 24 529516376 ps
T125 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2224236991 Aug 17 05:07:08 PM PDT 24 Aug 17 05:07:10 PM PDT 24 680145604 ps
T952 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3013606482 Aug 17 05:07:22 PM PDT 24 Aug 17 05:07:24 PM PDT 24 71646506 ps
T953 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1257332515 Aug 17 05:07:07 PM PDT 24 Aug 17 05:07:08 PM PDT 24 29099424 ps
T954 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4052779773 Aug 17 05:06:47 PM PDT 24 Aug 17 05:06:48 PM PDT 24 40217105 ps
T100 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2114775165 Aug 17 05:07:56 PM PDT 24 Aug 17 05:07:57 PM PDT 24 22381546 ps
T955 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2901648042 Aug 17 05:07:22 PM PDT 24 Aug 17 05:07:23 PM PDT 24 17802005 ps
T956 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.814900366 Aug 17 05:07:10 PM PDT 24 Aug 17 05:07:12 PM PDT 24 254710814 ps
T957 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3975742041 Aug 17 05:07:08 PM PDT 24 Aug 17 05:07:09 PM PDT 24 16313119 ps
T958 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4175454390 Aug 17 05:07:29 PM PDT 24 Aug 17 05:07:30 PM PDT 24 23877666 ps
T959 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2215168398 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:40 PM PDT 24 171359459 ps
T960 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3521139101 Aug 17 05:07:06 PM PDT 24 Aug 17 05:07:07 PM PDT 24 53010479 ps
T102 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2411129818 Aug 17 05:07:06 PM PDT 24 Aug 17 05:07:07 PM PDT 24 20099441 ps
T961 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.39108462 Aug 17 05:07:45 PM PDT 24 Aug 17 05:07:47 PM PDT 24 94373669 ps
T962 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2711583436 Aug 17 05:07:55 PM PDT 24 Aug 17 05:07:56 PM PDT 24 25340738 ps
T96 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2754956826 Aug 17 05:07:31 PM PDT 24 Aug 17 05:07:32 PM PDT 24 21770242 ps
T963 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.703753897 Aug 17 05:07:14 PM PDT 24 Aug 17 05:07:17 PM PDT 24 357067724 ps
T964 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2370979359 Aug 17 05:07:31 PM PDT 24 Aug 17 05:07:34 PM PDT 24 1639533218 ps
T965 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3604417336 Aug 17 05:07:46 PM PDT 24 Aug 17 05:07:48 PM PDT 24 67880712 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3919110233 Aug 17 05:06:56 PM PDT 24 Aug 17 05:06:57 PM PDT 24 52500504 ps
T967 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2893327127 Aug 17 05:07:14 PM PDT 24 Aug 17 05:07:16 PM PDT 24 115294064 ps
T968 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1381015277 Aug 17 05:07:47 PM PDT 24 Aug 17 05:07:50 PM PDT 24 722675841 ps
T969 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1498509764 Aug 17 05:06:57 PM PDT 24 Aug 17 05:06:58 PM PDT 24 14039182 ps
T970 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3153027660 Aug 17 05:07:22 PM PDT 24 Aug 17 05:07:23 PM PDT 24 25769059 ps
T971 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.822487131 Aug 17 05:07:56 PM PDT 24 Aug 17 05:07:57 PM PDT 24 57986566 ps
T97 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1975293061 Aug 17 05:08:00 PM PDT 24 Aug 17 05:08:03 PM PDT 24 530761104 ps
T972 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3303438627 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:35 PM PDT 24 305102215 ps
T973 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4183597935 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:32 PM PDT 24 49787633 ps
T974 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2518731707 Aug 17 05:07:33 PM PDT 24 Aug 17 05:07:37 PM PDT 24 1534889239 ps
T975 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2615000742 Aug 17 05:07:56 PM PDT 24 Aug 17 05:07:58 PM PDT 24 62171045 ps
T976 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1953442021 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:41 PM PDT 24 241853396 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.664010148 Aug 17 05:06:58 PM PDT 24 Aug 17 05:07:03 PM PDT 24 2583158339 ps
T978 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.643739801 Aug 17 05:06:49 PM PDT 24 Aug 17 05:06:51 PM PDT 24 21035549 ps
T979 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1550237774 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:31 PM PDT 24 66023198 ps
T980 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2844800052 Aug 17 05:06:57 PM PDT 24 Aug 17 05:07:00 PM PDT 24 1046230041 ps
T981 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1720496670 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:34 PM PDT 24 202610146 ps
T123 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2436720797 Aug 17 05:07:20 PM PDT 24 Aug 17 05:07:22 PM PDT 24 148619339 ps
T982 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2355905476 Aug 17 05:07:48 PM PDT 24 Aug 17 05:07:49 PM PDT 24 12463588 ps
T98 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2435818714 Aug 17 05:06:58 PM PDT 24 Aug 17 05:07:02 PM PDT 24 1583574521 ps
T983 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1199029014 Aug 17 05:07:47 PM PDT 24 Aug 17 05:07:50 PM PDT 24 321192545 ps
T984 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1184257370 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:41 PM PDT 24 2706359141 ps
T985 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.117573427 Aug 17 05:06:57 PM PDT 24 Aug 17 05:06:57 PM PDT 24 17936683 ps
T986 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2225284666 Aug 17 05:07:06 PM PDT 24 Aug 17 05:07:07 PM PDT 24 71433369 ps
T987 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1422294105 Aug 17 05:07:24 PM PDT 24 Aug 17 05:07:25 PM PDT 24 43885875 ps
T988 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.790506352 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:31 PM PDT 24 12920532 ps
T989 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1952816747 Aug 17 05:06:57 PM PDT 24 Aug 17 05:06:58 PM PDT 24 35710011 ps
T990 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1119323995 Aug 17 05:07:08 PM PDT 24 Aug 17 05:07:09 PM PDT 24 257214489 ps
T991 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2978793817 Aug 17 05:07:47 PM PDT 24 Aug 17 05:07:50 PM PDT 24 829816429 ps
T992 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1884288039 Aug 17 05:07:30 PM PDT 24 Aug 17 05:07:35 PM PDT 24 136653224 ps
T993 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3468715188 Aug 17 05:07:22 PM PDT 24 Aug 17 05:07:23 PM PDT 24 31112725 ps
T120 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1309089791 Aug 17 05:07:14 PM PDT 24 Aug 17 05:07:16 PM PDT 24 140911330 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1345983790 Aug 17 05:06:55 PM PDT 24 Aug 17 05:06:56 PM PDT 24 50997426 ps
T995 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1535754459 Aug 17 05:07:48 PM PDT 24 Aug 17 05:07:49 PM PDT 24 39073346 ps
T996 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.232214880 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:39 PM PDT 24 55142200 ps
T997 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4262556621 Aug 17 05:07:40 PM PDT 24 Aug 17 05:07:41 PM PDT 24 29190504 ps
T130 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2170479668 Aug 17 05:07:50 PM PDT 24 Aug 17 05:07:53 PM PDT 24 662529382 ps
T99 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1157611424 Aug 17 05:06:58 PM PDT 24 Aug 17 05:07:02 PM PDT 24 1572483071 ps
T998 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1242224297 Aug 17 05:06:57 PM PDT 24 Aug 17 05:06:58 PM PDT 24 27414596 ps
T999 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3694769220 Aug 17 05:07:14 PM PDT 24 Aug 17 05:07:14 PM PDT 24 53257258 ps
T1000 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2239734595 Aug 17 05:07:38 PM PDT 24 Aug 17 05:07:39 PM PDT 24 28891790 ps
T1001 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3556750147 Aug 17 05:07:39 PM PDT 24 Aug 17 05:07:43 PM PDT 24 223917537 ps
T1002 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4153043431 Aug 17 05:07:06 PM PDT 24 Aug 17 05:07:10 PM PDT 24 206371145 ps
T1003 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3087227837 Aug 17 05:07:25 PM PDT 24 Aug 17 05:07:26 PM PDT 24 16417623 ps
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