Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13883902

1

T2

1125

T3

16

T4

885

full_word

55873353

1

T2

288

T3

157

T4

53

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69756945	1			T2	1413		T3	173		T4	938
auto[TlIntgErrCmd]	105	1			T49	13		T50	5		T51	3
auto[TlIntgErrData]	105	1			T49	1		T50	4		T51	4
auto[TlIntgErrBoth]	100	1			T49	6		T50	11		T51	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31841607

1

T2

712

T3

93

T4

346

auto[1]

37915648

1

T2

701

T3

80

T4

592

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6622375	1			T2	562		T3	10		T4	343
auto[TlIntgErrNone]	partial	auto[1]	7261243	1			T2	563		T3	6		T4	542
auto[TlIntgErrNone]	full_word	auto[0]	25219111	1			T2	150		T3	83		T4	3
auto[TlIntgErrNone]	full_word	auto[1]	30654216	1			T2	138		T3	74		T4	50
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T49	4		T50	2		T109	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T49	9		T50	3		T51	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T109	1		T114	2		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T118	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T49	1		T50	2		T51	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T50	2		T51	1		T109	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T110	1		T119	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T51	1		T114	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T50	3		T51	1		T109	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T49	6		T50	7		T51	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T117	2		T121	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T50	1		T110	1		T119	1