Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	657540	1			T29	16		T30	87		T31	16
auto[1]	10873994	1			T2	650		T3	83		T9	17
auto[2]	548771	1			T29	5		T30	69		T31	7
auto[3]	10770567	1			T2	643		T3	70		T9	16

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15054285	1			T2	61		T3	124		T27	7
auto[1]	2154240	1			T2	206		T3	16		T9	5
auto[2]	2176321	1			T2	180		T3	13		T9	2
auto[3]	3466026	1			T2	846		T9	26		T27	717

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9914508

1

T2

1290

T3

153

T9

33

auto[1]

12936364

1

T2

3

T27

2

T28

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	261789	1			T29	14		T31	12		T21	542
auto[0]	auto[0]	auto[1]	26988	1			T31	2		T21	56		T36	13
auto[0]	auto[0]	auto[2]	27008	1			T29	2		T30	1		T31	2
auto[0]	auto[0]	auto[3]	7358	1			T30	84		T21	6		T36	1
auto[0]	auto[1]	auto[0]	3819220	1			T2	31		T3	64		T28	237
auto[0]	auto[1]	auto[1]	392956	1			T2	98		T3	10		T9	4
auto[0]	auto[1]	auto[2]	385612	1			T2	84		T3	9		T27	42
auto[0]	auto[1]	auto[3]	78223	1			T2	435		T9	13		T27	275
auto[0]	auto[2]	auto[0]	225750	1			T21	526		T36	113		T106	10
auto[0]	auto[2]	auto[1]	23525	1			T30	13		T21	40		T36	12
auto[0]	auto[2]	auto[2]	24328	1			T29	4		T31	7		T21	41
auto[0]	auto[2]	auto[3]	5998	1			T29	1		T30	56		T21	6
auto[0]	auto[3]	auto[0]	3784370	1			T2	30		T3	60		T27	7
auto[0]	auto[3]	auto[1]	381823	1			T2	107		T3	6		T9	1
auto[0]	auto[3]	auto[2]	391272	1			T2	96		T3	4		T9	2
auto[0]	auto[3]	auto[3]	78288	1			T2	409		T9	13		T27	440
auto[1]	auto[0]	auto[0]	11468	1			T21	1		T95	91		T97	139
auto[1]	auto[0]	auto[1]	49607	1			T95	423		T97	599		T133	3428
auto[1]	auto[0]	auto[2]	49666	1			T21	1		T95	427		T97	570
auto[1]	auto[0]	auto[3]	223656	1			T30	2		T95	1949		T97	2665
auto[1]	auto[1]	auto[0]	3473622	1			T28	1		T61	4		T62	3
auto[1]	auto[1]	auto[1]	639726	1			T2	1		T32	1		T134	1
auto[1]	auto[1]	auto[2]	624253	1			T134	1		T135	1		T136	1
auto[1]	auto[1]	auto[3]	1460382	1			T2	1		T64	2		T136	4
auto[1]	auto[2]	auto[0]	7742	1			T137	1		T133	705		T138	842
auto[1]	auto[2]	auto[1]	32600	1			T133	3156		T138	3759		T139	2829
auto[1]	auto[2]	auto[2]	41708	1			T95	399		T97	515		T133	2808
auto[1]	auto[2]	auto[3]	187120	1			T95	1786		T97	2415		T133	12786
auto[1]	auto[3]	auto[0]	3470324	1			T32	1		T7	2		T31	1
auto[1]	auto[3]	auto[1]	607015	1			T61	1		T134	1		T140	1
auto[1]	auto[3]	auto[2]	632474	1			T136	1		T92	3490		T141	1
auto[1]	auto[3]	auto[3]	1425001	1			T2	1		T27	2		T134	1