Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	301660136	201752	0	0
ctrl_regwen_rd_A	301660136	4592	0	0
exec_rd_A	301660136	4158	0	0
exec_regwen_rd_A	301660136	4649	0	0
readback_rd_A	301660136	2806	0	0
readback_regwen_rd_A	301660136	2443	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301660136	201752	0	0
T17	0	2634	0	0
T18	0	3180	0	0
T19	0	2405	0	0
T20	28903	0	0	0
T21	78129	1732	0	0
T22	0	1235	0	0
T25	19934	0	0	0
T42	0	3053	0	0
T48	0	5228	0	0
T53	58180	0	0	0
T58	0	3513	0	0
T59	0	12062	0	0
T60	0	5324	0	0
T61	10417	0	0	0
T62	9962	0	0	0
T63	2102	0	0	0
T64	5944	0	0	0
T65	1473	0	0	0
T66	51195	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301660136	4592	0	0
T20	28903	0	0	0
T21	78129	152	0	0
T25	19934	0	0	0
T42	0	123	0	0
T43	0	46	0	0
T48	0	319	0	0
T53	58180	0	0	0
T58	0	236	0	0
T61	10417	0	0	0
T62	9962	0	0	0
T63	2102	0	0	0
T64	5944	0	0	0
T65	1473	0	0	0
T66	51195	0	0	0
T101	0	416	0	0
T102	0	371	0	0
T103	0	129	0	0
T104	0	367	0	0
T105	0	274	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301660136	4158	0	0
T20	28903	0	0	0
T21	78129	88	0	0
T25	19934	0	0	0
T42	0	108	0	0
T43	0	85	0	0
T48	0	366	0	0
T53	58180	0	0	0
T58	0	182	0	0
T61	10417	0	0	0
T62	9962	0	0	0
T63	2102	0	0	0
T64	5944	0	0	0
T65	1473	0	0	0
T66	51195	0	0	0
T101	0	371	0	0
T102	0	269	0	0
T103	0	140	0	0
T104	0	223	0	0
T105	0	282	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301660136	4649	0	0
T20	28903	0	0	0
T21	78129	134	0	0
T25	19934	0	0	0
T42	0	113	0	0
T43	0	49	0	0
T48	0	365	0	0
T53	58180	0	0	0
T58	0	217	0	0
T61	10417	0	0	0
T62	9962	0	0	0
T63	2102	0	0	0
T64	5944	0	0	0
T65	1473	0	0	0
T66	51195	0	0	0
T101	0	539	0	0
T102	0	385	0	0
T103	0	101	0	0
T104	0	271	0	0
T105	0	296	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301660136	2806	0	0
T20	28903	0	0	0
T21	78129	85	0	0
T25	19934	0	0	0
T42	0	145	0	0
T43	0	59	0	0
T48	0	343	0	0
T53	58180	0	0	0
T58	0	173	0	0
T61	10417	0	0	0
T62	9962	0	0	0
T63	2102	0	0	0
T64	5944	0	0	0
T65	1473	0	0	0
T66	51195	0	0	0
T101	0	425	0	0
T102	0	314	0	0
T103	0	107	0	0
T104	0	328	0	0
T105	0	231	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301660136	2443	0	0
T20	28903	0	0	0
T21	78129	89	0	0
T25	19934	0	0	0
T42	0	109	0	0
T43	0	68	0	0
T48	0	203	0	0
T53	58180	0	0	0
T58	0	147	0	0
T61	10417	0	0	0
T62	9962	0	0	0
T63	2102	0	0	0
T64	5944	0	0	0
T65	1473	0	0	0
T66	51195	0	0	0
T101	0	371	0	0
T102	0	269	0	0
T103	0	106	0	0
T104	0	251	0	0
T105	0	243	0	0