Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13428715

1

T2

222

T5

82

T8

1762

full_word

54104176

1

T2

1104

T4

3071

T5

841

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67532591	1			T2	1326		T4	3071		T5	923
auto[TlIntgErrCmd]	101	1			T52	2		T53	5		T54	5
auto[TlIntgErrData]	99	1			T52	3		T53	7		T54	9
auto[TlIntgErrBoth]	100	1			T52	5		T53	8		T54	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30919046

1

T2

628

T4

1024

T5

465

auto[1]

36613845

1

T2

698

T4

2047

T5

458

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6414734	1			T2	99		T5	32		T8	825
auto[TlIntgErrNone]	partial	auto[1]	7013705	1			T2	123		T5	50		T8	937
auto[TlIntgErrNone]	full_word	auto[0]	24504182	1			T2	529		T4	1024		T5	433
auto[TlIntgErrNone]	full_word	auto[1]	29599970	1			T2	575		T4	2047		T5	408
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T52	1		T53	1		T54	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T52	1		T53	4		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T117	1		T122	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T122	1		T118	1		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T52	3		T53	1		T54	6
auto[TlIntgErrData]	partial	auto[1]	44	1			T53	5		T54	3		T115	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T123	2		T120	2		T121	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T53	1		T116	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T52	2		T53	3		T54	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T52	3		T53	4		T54	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T124	1		T120	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T53	1		T115	1		T116	1