Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	772887	1			T12	5		T30	53		T38	903
auto[1]	10477699	1			T2	628		T6	6		T10	226
auto[2]	636426	1			T6	1		T12	5		T30	31
auto[3]	10351336	1			T2	697		T6	3		T10	207

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14491857	1			T2	925		T6	8		T10	274
auto[1]	2108447	1			T2	178		T10	77		T12	3
auto[2]	2116395	1			T2	182		T6	2		T10	62
auto[3]	3521649	1			T2	40		T10	20		T7	7

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8949578

1

T2

1324

T6

10

T10

432

auto[1]

13288770

1

T2

1

T10

1

T29

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	290015	1			T12	3		T38	21		T63	5
auto[0]	auto[0]	auto[1]	30871	1			T12	2		T30	1		T38	135
auto[0]	auto[0]	auto[2]	31064	1			T38	140		T39	1		T63	1
auto[0]	auto[0]	auto[3]	11596	1			T30	51		T38	607		T39	20
auto[0]	auto[1]	auto[0]	3403475	1			T2	445		T6	5		T10	139
auto[0]	auto[1]	auto[1]	348763	1			T2	84		T10	44		T7	44
auto[0]	auto[1]	auto[2]	338878	1			T2	86		T6	1		T10	30
auto[0]	auto[1]	auto[3]	71605	1			T2	12		T10	13		T7	4
auto[0]	auto[2]	auto[0]	247028	1			T12	3		T38	27		T20	1033
auto[0]	auto[2]	auto[1]	25931	1			T12	1		T38	111		T63	2
auto[0]	auto[2]	auto[2]	27016	1			T6	1		T12	1		T38	92
auto[0]	auto[2]	auto[3]	9617	1			T30	31		T38	393		T39	9
auto[0]	auto[3]	auto[0]	3360927	1			T2	480		T6	3		T10	134
auto[0]	auto[3]	auto[1]	335066	1			T2	94		T10	33		T28	1
auto[0]	auto[3]	auto[2]	346160	1			T2	95		T10	32		T28	1
auto[0]	auto[3]	auto[3]	71566	1			T2	28		T10	7		T7	3
auto[1]	auto[0]	auto[0]	13565	1			T100	481		T137	1		T103	417
auto[1]	auto[0]	auto[1]	61205	1			T20	1		T100	2237		T103	2054
auto[1]	auto[0]	auto[2]	60706	1			T30	1		T100	2159		T103	1958
auto[1]	auto[0]	auto[3]	273865	1			T100	9808		T78	1		T103	8968
auto[1]	auto[1]	auto[0]	3583397	1			T29	2		T138	3		T32	1
auto[1]	auto[1]	auto[1]	650568	1			T96	4891		T97	6978		T98	5955
auto[1]	auto[1]	auto[2]	625226	1			T2	1		T96	5344		T97	6920
auto[1]	auto[1]	auto[3]	1455787	1			T38	2		T139	5		T89	3
auto[1]	auto[2]	auto[0]	10492	1			T20	2		T100	407		T125	2
auto[1]	auto[2]	auto[1]	46255	1			T100	2073		T103	1193		T140	2071
auto[1]	auto[2]	auto[2]	49219	1			T100	1840		T103	2102		T141	617
auto[1]	auto[2]	auto[3]	220868	1			T38	1		T100	8334		T103	9611
auto[1]	auto[3]	auto[0]	3582958	1			T10	1		T29	1		T138	2
auto[1]	auto[3]	auto[1]	609788	1			T142	1		T96	5415		T97	6922
auto[1]	auto[3]	auto[2]	638126	1			T143	1		T139	2		T144	1
auto[1]	auto[3]	auto[3]	1406745	1			T139	2		T89	2		T96	450