Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	317774622	188677	0	0
ctrl_regwen_rd_A	317774622	3934	0	0
exec_rd_A	317774622	3180	0	0
exec_regwen_rd_A	317774622	3617	0	0
readback_rd_A	317774622	2046	0	0
readback_regwen_rd_A	317774622	1840	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317774622	188677	0	0
T7	52035	0	0	0
T12	24714	1128	0	0
T13	1928	0	0	0
T16	11413	0	0	0
T20	0	3900	0	0
T21	0	1953	0	0
T23	0	4754	0	0
T24	3073	0	0	0
T28	12465	0	0	0
T29	6195	0	0	0
T30	14735	0	0	0
T31	65439	0	0	0
T43	39995	0	0	0
T48	0	1288	0	0
T49	0	3710	0	0
T51	0	3441	0	0
T64	0	9077	0	0
T65	0	5746	0	0
T66	0	741	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317774622	3934	0	0
T20	221799	362	0	0
T21	47084	0	0	0
T27	8171	0	0	0
T41	0	282	0	0
T42	0	208	0	0
T46	8491	0	0	0
T47	33480	0	0	0
T48	0	102	0	0
T57	179572	0	0	0
T61	0	49	0	0
T96	190286	0	0	0
T97	219682	0	0	0
T107	0	368	0	0
T108	0	174	0	0
T109	0	238	0	0
T110	0	348	0	0
T111	0	290	0	0
T112	3740	0	0	0
T113	1205	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317774622	3180	0	0
T20	221799	230	0	0
T21	47084	0	0	0
T27	8171	0	0	0
T41	0	204	0	0
T42	0	213	0	0
T46	8491	0	0	0
T47	33480	0	0	0
T48	0	90	0	0
T57	179572	0	0	0
T61	0	33	0	0
T96	190286	0	0	0
T97	219682	0	0	0
T107	0	219	0	0
T108	0	155	0	0
T109	0	208	0	0
T110	0	283	0	0
T111	0	243	0	0
T112	3740	0	0	0
T113	1205	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317774622	3617	0	0
T20	221799	307	0	0
T21	47084	0	0	0
T27	8171	0	0	0
T41	0	217	0	0
T42	0	262	0	0
T46	8491	0	0	0
T47	33480	0	0	0
T48	0	102	0	0
T57	179572	0	0	0
T61	0	46	0	0
T96	190286	0	0	0
T97	219682	0	0	0
T107	0	338	0	0
T108	0	113	0	0
T109	0	308	0	0
T110	0	317	0	0
T111	0	271	0	0
T112	3740	0	0	0
T113	1205	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317774622	2046	0	0
T20	221799	230	0	0
T21	47084	0	0	0
T27	8171	0	0	0
T41	0	211	0	0
T42	0	214	0	0
T46	8491	0	0	0
T47	33480	0	0	0
T48	0	70	0	0
T57	179572	0	0	0
T96	190286	0	0	0
T97	219682	0	0	0
T107	0	244	0	0
T108	0	107	0	0
T109	0	194	0	0
T110	0	253	0	0
T111	0	271	0	0
T112	3740	0	0	0
T113	1205	0	0	0
T114	0	4	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317774622	1840	0	0
T20	221799	239	0	0
T21	47084	0	0	0
T27	8171	0	0	0
T41	0	95	0	0
T42	0	173	0	0
T46	8491	0	0	0
T47	33480	0	0	0
T48	0	51	0	0
T57	179572	0	0	0
T96	190286	0	0	0
T97	219682	0	0	0
T107	0	260	0	0
T108	0	134	0	0
T109	0	163	0	0
T110	0	210	0	0
T111	0	324	0	0
T112	3740	0	0	0
T113	1205	0	0	0
T114	0	2	0	0