Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14735710

1

T3

35

T4

42

T7

1878

full_word

57556269

1

T3

406

T4

431

T5

3071

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	72291699	1			T3	441		T4	473		T5	3071
auto[TlIntgErrCmd]	89	1			T56	8		T57	2		T58	1
auto[TlIntgErrData]	85	1			T56	8		T57	3		T58	6
auto[TlIntgErrBoth]	106	1			T56	4		T57	5		T58	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32904705

1

T3

210

T4

242

T5

1024

auto[1]

39387274

1

T3

231

T4

231

T5

2047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7023281	1			T3	17		T4	23		T7	902
auto[TlIntgErrNone]	partial	auto[1]	7712178	1			T3	18		T4	19		T7	976
auto[TlIntgErrNone]	full_word	auto[0]	25881298	1			T3	193		T4	219		T5	1024
auto[TlIntgErrNone]	full_word	auto[1]	31674942	1			T3	213		T4	212		T5	2047
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T56	1		T58	1		T137	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T56	7		T57	2		T137	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T137	1		T142	2		T144	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T135	2		T136	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T56	1		T57	1		T58	3
auto[TlIntgErrData]	partial	auto[1]	34	1			T56	5		T57	2		T58	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T138	1		T144	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T56	2		T58	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T56	3		T57	5		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T58	1		T137	8		T135	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T56	1		T135	1		T146	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T135	1		T147	1		T144	1