Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	595448	1			T9	23		T34	11		T19	19
auto[1]	10742641	1			T6	3		T11	18		T9	7
auto[2]	466313	1			T6	1		T9	19		T34	11
auto[3]	10613077	1			T6	7		T11	12		T9	3

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14218786	1			T6	8		T9	41		T21	37
auto[1]	2167108	1			T6	1		T11	3		T9	5
auto[2]	2185677	1			T6	2		T11	1		T9	3
auto[3]	3845908	1			T11	26		T9	3		T21	3

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8527275

1

T6

11

T11

30

T9

52

auto[1]

13890204

1

T53

7

T105

1

T54

9

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	162537	1			T9	15		T19	17		T164	11
auto[0]	auto[0]	auto[1]	17477	1			T9	3		T19	1		T165	10
auto[0]	auto[0]	auto[2]	17309	1			T9	2		T19	1		T164	1
auto[0]	auto[0]	auto[3]	8452	1			T9	3		T34	11		T165	58
auto[0]	auto[1]	auto[0]	3341740	1			T6	1		T9	5		T21	18
auto[0]	auto[1]	auto[1]	342358	1			T6	1		T11	3		T9	2
auto[0]	auto[1]	auto[2]	338514	1			T6	1		T21	7		T34	3
auto[0]	auto[1]	auto[3]	70478	1			T11	15		T21	3		T27	6
auto[0]	auto[2]	auto[0]	129259	1			T9	18		T19	20		T72	10
auto[0]	auto[2]	auto[1]	13856	1			T19	4		T72	64		T17	11
auto[0]	auto[2]	auto[2]	19322	1			T6	1		T9	1		T19	5
auto[0]	auto[2]	auto[3]	7272	1			T34	11		T165	33		T69	26
auto[0]	auto[3]	auto[0]	3308451	1			T6	7		T9	3		T21	19
auto[0]	auto[3]	auto[1]	334795	1			T21	4		T27	1		T34	2
auto[0]	auto[3]	auto[2]	343521	1			T11	1		T21	3		T27	1
auto[0]	auto[3]	auto[3]	71934	1			T11	11		T27	6		T34	123
auto[1]	auto[0]	auto[0]	13006	1			T166	2		T162	367		T163	144
auto[1]	auto[0]	auto[1]	58403	1			T167	1		T162	1660		T163	684
auto[1]	auto[0]	auto[2]	58404	1			T162	1689		T163	676		T168	941
auto[1]	auto[0]	auto[3]	259860	1			T165	1		T92	2		T162	7429
auto[1]	auto[1]	auto[0]	3629925	1			T53	2		T54	2		T55	3
auto[1]	auto[1]	auto[1]	697403	1			T55	2		T169	1		T75	3884
auto[1]	auto[1]	auto[2]	678049	1			T54	1		T75	4237		T170	1
auto[1]	auto[1]	auto[3]	1644174	1			T68	2		T73	1		T75	392
auto[1]	auto[2]	auto[0]	9569	1			T17	1		T171	1		T166	3
auto[1]	auto[2]	auto[1]	42283	1			T162	1004		T172	3556		T173	2739
auto[1]	auto[2]	auto[2]	44503	1			T166	1		T162	1815		T163	617
auto[1]	auto[2]	auto[3]	200249	1			T92	1		T162	8149		T163	2744
auto[1]	auto[3]	auto[0]	3624299	1			T53	5		T105	1		T54	5
auto[1]	auto[3]	auto[1]	660533	1			T68	2		T73	2		T75	4208
auto[1]	auto[3]	auto[2]	686055	1			T54	1		T55	2		T73	1
auto[1]	auto[3]	auto[3]	1583489	1			T90	1		T72	2		T75	408