Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	323333679	231991	0	0
ctrl_regwen_rd_A	323333679	2817	0	0
exec_rd_A	323333679	2576	0	0
exec_regwen_rd_A	323333679	2554	0	0
readback_rd_A	323333679	1765	0	0
readback_regwen_rd_A	323333679	1708	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323333679	231991	0	0
T16	195865	6340	0	0
T18	0	10255	0	0
T22	42872	3461	0	0
T23	0	1433	0	0
T51	0	5249	0	0
T63	0	6595	0	0
T64	0	3747	0	0
T65	0	11312	0	0
T66	0	1538	0	0
T67	0	7333	0	0
T68	15106	0	0	0
T69	14400	0	0	0
T70	772	0	0	0
T71	58942	0	0	0
T72	68478	0	0	0
T73	15446	0	0	0
T74	15355	0	0	0
T75	147339	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323333679	2817	0	0
T44	57330	51	0	0
T45	0	70	0	0
T46	0	397	0	0
T118	0	385	0	0
T119	0	130	0	0
T120	0	302	0	0
T121	0	161	0	0
T122	0	68	0	0
T123	0	87	0	0
T124	0	210	0	0
T125	162968	0	0	0
T126	2596	0	0	0
T127	14199	0	0	0
T128	87737	0	0	0
T129	266263	0	0	0
T130	5800	0	0	0
T131	249791	0	0	0
T132	13021	0	0	0
T133	93520	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323333679	2576	0	0
T44	57330	60	0	0
T45	0	67	0	0
T46	0	403	0	0
T118	0	202	0	0
T119	0	152	0	0
T120	0	247	0	0
T121	0	164	0	0
T122	0	93	0	0
T123	0	106	0	0
T124	0	222	0	0
T125	162968	0	0	0
T126	2596	0	0	0
T127	14199	0	0	0
T128	87737	0	0	0
T129	266263	0	0	0
T130	5800	0	0	0
T131	249791	0	0	0
T132	13021	0	0	0
T133	93520	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323333679	2554	0	0
T44	57330	52	0	0
T45	0	73	0	0
T46	0	341	0	0
T118	0	264	0	0
T119	0	128	0	0
T120	0	240	0	0
T121	0	134	0	0
T122	0	66	0	0
T123	0	70	0	0
T124	0	223	0	0
T125	162968	0	0	0
T126	2596	0	0	0
T127	14199	0	0	0
T128	87737	0	0	0
T129	266263	0	0	0
T130	5800	0	0	0
T131	249791	0	0	0
T132	13021	0	0	0
T133	93520	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323333679	1765	0	0
T44	57330	40	0	0
T45	0	45	0	0
T46	0	438	0	0
T118	0	222	0	0
T119	0	110	0	0
T120	0	170	0	0
T121	0	131	0	0
T122	0	75	0	0
T123	0	49	0	0
T124	0	194	0	0
T125	162968	0	0	0
T126	2596	0	0	0
T127	14199	0	0	0
T128	87737	0	0	0
T129	266263	0	0	0
T130	5800	0	0	0
T131	249791	0	0	0
T132	13021	0	0	0
T133	93520	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323333679	1708	0	0
T44	57330	102	0	0
T45	0	46	0	0
T46	0	351	0	0
T118	0	220	0	0
T119	0	123	0	0
T120	0	231	0	0
T121	0	119	0	0
T122	0	55	0	0
T123	0	50	0	0
T124	0	187	0	0
T125	162968	0	0	0
T126	2596	0	0	0
T127	14199	0	0	0
T128	87737	0	0	0
T129	266263	0	0	0
T130	5800	0	0	0
T131	249791	0	0	0
T132	13021	0	0	0
T133	93520	0	0	0