Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14381959

1

T3

51

T4

36

T5

975

full_word

55358867

1

T3

256

T4

469

T5

42

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69740536	1			T3	307		T4	505		T5	1017
auto[TlIntgErrCmd]	83	1			T63	5		T64	4		T124	6
auto[TlIntgErrData]	111	1			T62	6		T63	10		T64	5
auto[TlIntgErrBoth]	96	1			T62	4		T63	5		T64	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31908963

1

T3

167

T4

255

T5

388

auto[1]

37831863

1

T3

140

T4

250

T5

629

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6879797	1			T3	33		T4	15		T5	387
auto[TlIntgErrNone]	partial	auto[1]	7501905	1			T3	18		T4	21		T5	588
auto[TlIntgErrNone]	full_word	auto[0]	25029028	1			T3	134		T4	240		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	30329806	1			T3	122		T4	229		T5	41
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T63	1		T64	1		T124	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T63	4		T64	1		T124	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T64	2		T126	1		T132	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T126	1		T133	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T62	3		T63	5		T64	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T62	2		T63	3		T64	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T63	1		T125	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T62	1		T63	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T62	3		T63	2		T124	2
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T62	1		T63	2		T64	1
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T63	1		T124	2		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T134	1		T126	1		T127	1