Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	728505	1			T5	28		T8	4		T33	252
auto[1]	10618209	1			T3	167		T5	53		T8	6
auto[2]	600578	1			T5	12		T8	3		T33	196
auto[3]	10490574	1			T3	139		T5	121		T8	3

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14211320	1			T3	230		T7	629		T9	536
auto[1]	2170250	1			T3	26		T8	1		T7	45
auto[2]	2187066	1			T3	47		T5	9		T8	1
auto[3]	3869230	1			T3	3		T5	205		T8	14

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8522980

1

T3

305

T5

214

T8

16

auto[1]

13914886

1

T3

1

T7

2

T33

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	315683	1			T23	138		T68	13		T60	3
auto[0]	auto[0]	auto[1]	32156	1			T8	1		T23	12		T68	2
auto[0]	auto[0]	auto[2]	32105	1			T33	2		T23	20		T20	1
auto[0]	auto[0]	auto[3]	8720	1			T5	28		T8	3		T33	246
auto[0]	auto[1]	auto[0]	3206375	1			T3	124		T7	307		T9	225
auto[0]	auto[1]	auto[1]	334398	1			T3	9		T7	19		T33	3
auto[0]	auto[1]	auto[2]	321381	1			T3	31		T7	33		T33	4
auto[0]	auto[1]	auto[3]	63219	1			T3	2		T5	53		T8	6
auto[0]	auto[2]	auto[0]	270231	1			T23	130		T68	12		T60	7
auto[0]	auto[2]	auto[1]	27366	1			T33	19		T23	14		T68	1
auto[0]	auto[2]	auto[2]	29361	1			T8	1		T23	10		T68	1
auto[0]	auto[2]	auto[3]	7070	1			T5	12		T8	2		T33	177
auto[0]	auto[3]	auto[0]	3162694	1			T3	105		T7	320		T9	311
auto[0]	auto[3]	auto[1]	316492	1			T3	17		T7	26		T33	1
auto[0]	auto[3]	auto[2]	332107	1			T3	16		T5	9		T7	23
auto[0]	auto[3]	auto[3]	63622	1			T3	1		T5	112		T8	3
auto[1]	auto[0]	auto[0]	11545	1			T152	1		T153	1		T55	1
auto[1]	auto[0]	auto[1]	50546	1			T153	2		T150	726		T154	4723
auto[1]	auto[0]	auto[2]	50763	1			T150	703		T154	4842		T155	2
auto[1]	auto[0]	auto[3]	226987	1			T33	4		T88	1		T150	3195
auto[1]	auto[1]	auto[0]	3622354	1			T3	1		T7	2		T27	4
auto[1]	auto[1]	auto[1]	703788	1			T29	1		T156	1		T65	1
auto[1]	auto[1]	auto[2]	688367	1			T103	4414		T157	1		T53	2
auto[1]	auto[1]	auto[3]	1678327	1			T87	2		T103	441		T158	1
auto[1]	auto[2]	auto[0]	7995	1			T152	1		T153	4		T138	4
auto[1]	auto[2]	auto[1]	34361	1			T153	1		T154	4459		T159	2383
auto[1]	auto[2]	auto[2]	41050	1			T150	657		T154	4023		T159	1781
auto[1]	auto[2]	auto[3]	183144	1			T150	2864		T154	18495		T159	7669
auto[1]	auto[3]	auto[0]	3614443	1			T27	2		T22	5		T29	2
auto[1]	auto[3]	auto[1]	671143	1			T29	1		T61	1		T103	4499
auto[1]	auto[3]	auto[2]	691932	1			T61	1		T103	4491		T104	5091
auto[1]	auto[3]	auto[3]	1638141	1			T87	2		T103	452		T158	1