Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	341610746	194639	0	0
ctrl_regwen_rd_A	341610746	3803	0	0
exec_rd_A	341610746	3782	0	0
exec_regwen_rd_A	341610746	3772	0	0
readback_rd_A	341610746	2349	0	0
readback_regwen_rd_A	341610746	1979	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341610746	194639	0	0
T10	49862	0	0	0
T14	928	0	0	0
T15	16508	0	0	0
T17	0	3239	0	0
T23	109272	3813	0	0
T24	0	1842	0	0
T25	0	2734	0	0
T30	2784	0	0	0
T40	0	3635	0	0
T53	0	4754	0	0
T54	0	4709	0	0
T55	0	7722	0	0
T68	32748	0	0	0
T69	0	1713	0	0
T70	0	1666	0	0
T71	950	0	0	0
T72	2904	0	0	0
T73	4501	0	0	0
T74	6034	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341610746	3803	0	0
T21	60362	0	0	0
T25	88798	133	0	0
T48	0	172	0	0
T50	0	463	0	0
T65	61097	0	0	0
T75	0	45	0	0
T88	9070	0	0	0
T111	0	327	0	0
T112	0	95	0	0
T113	0	65	0	0
T114	0	244	0	0
T115	0	546	0	0
T116	0	425	0	0
T117	84311	0	0	0
T118	4281	0	0	0
T119	16856	0	0	0
T120	2427	0	0	0
T121	12954	0	0	0
T122	541411	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341610746	3782	0	0
T21	60362	0	0	0
T25	88798	149	0	0
T48	0	205	0	0
T50	0	413	0	0
T65	61097	0	0	0
T75	0	36	0	0
T88	9070	0	0	0
T111	0	282	0	0
T112	0	218	0	0
T113	0	59	0	0
T114	0	246	0	0
T115	0	546	0	0
T116	0	321	0	0
T117	84311	0	0	0
T118	4281	0	0	0
T119	16856	0	0	0
T120	2427	0	0	0
T121	12954	0	0	0
T122	541411	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341610746	3772	0	0
T21	60362	0	0	0
T25	88798	185	0	0
T48	0	159	0	0
T50	0	450	0	0
T65	61097	0	0	0
T75	0	44	0	0
T88	9070	0	0	0
T111	0	315	0	0
T112	0	146	0	0
T113	0	49	0	0
T114	0	288	0	0
T115	0	478	0	0
T116	0	383	0	0
T117	84311	0	0	0
T118	4281	0	0	0
T119	16856	0	0	0
T120	2427	0	0	0
T121	12954	0	0	0
T122	541411	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341610746	2349	0	0
T21	60362	0	0	0
T25	88798	175	0	0
T48	0	143	0	0
T50	0	417	0	0
T65	61097	0	0	0
T88	9070	0	0	0
T111	0	284	0	0
T112	0	153	0	0
T113	0	50	0	0
T114	0	200	0	0
T115	0	393	0	0
T116	0	384	0	0
T117	84311	0	0	0
T118	4281	0	0	0
T119	16856	0	0	0
T120	2427	0	0	0
T121	12954	0	0	0
T122	541411	0	0	0
T123	0	51	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341610746	1979	0	0
T21	60362	0	0	0
T25	88798	165	0	0
T48	0	110	0	0
T50	0	324	0	0
T65	61097	0	0	0
T88	9070	0	0	0
T111	0	264	0	0
T112	0	112	0	0
T113	0	72	0	0
T114	0	182	0	0
T115	0	402	0	0
T116	0	270	0	0
T117	84311	0	0	0
T118	4281	0	0	0
T119	16856	0	0	0
T120	2427	0	0	0
T121	12954	0	0	0
T122	541411	0	0	0
T123	0	32	0	0