Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13888702

1

T3

1359

T4

58

T5

930

full_word

56007610

1

T3

290

T4

422

T5

61

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69895982	1			T3	1649		T4	480		T5	991
auto[TlIntgErrCmd]	110	1			T50	12		T51	6		T52	2
auto[TlIntgErrData]	115	1			T50	6		T51	7		T52	5
auto[TlIntgErrBoth]	105	1			T50	2		T51	7		T52	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32010931

1

T3

815

T4

249

T5

366

auto[1]

37885381

1

T3

834

T4

231

T5

625

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6637758	1			T3	668		T4	28		T5	363
auto[TlIntgErrNone]	partial	auto[1]	7250640	1			T3	691		T4	30		T5	567
auto[TlIntgErrNone]	full_word	auto[0]	25373027	1			T3	147		T4	221		T5	3
auto[TlIntgErrNone]	full_word	auto[1]	30634557	1			T3	143		T4	201		T5	58
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T50	5		T51	5		T52	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T50	6		T51	1		T133	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T130	1		T141	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T50	1		T136	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T50	5		T51	1		T52	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T50	1		T51	5		T133	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T129	1		T139	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T51	1		T133	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T50	1		T51	2		T52	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T51	3		T52	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T50	1		T51	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T51	1		T142	3		T132	1