Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	537976	1			T3	5		T6	1		T7	1
auto[1]	10663270	1			T3	4		T5	342		T6	2
auto[2]	456911	1			T3	2		T27	57		T31	84
auto[3]	10582733	1			T3	5		T5	556		T6	4

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14422188	1			T5	10		T6	2		T7	8
auto[1]	2118734	1			T3	3		T5	51		T27	34
auto[2]	2152805	1			T3	4		T5	91		T6	5
auto[3]	3547163	1			T3	9		T5	746		T27	143

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8788209

1

T3

16

T5

898

T6

7

auto[1]

13452681

1

T40

1

T47

2

T48

11

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	215969	1			T7	1		T27	3		T31	91
auto[0]	auto[0]	auto[1]	22558	1			T27	10		T31	8		T40	92
auto[0]	auto[0]	auto[2]	22796	1			T3	1		T6	1		T27	14
auto[0]	auto[0]	auto[3]	8525	1			T3	4		T27	38		T31	1
auto[0]	auto[1]	auto[0]	3402881	1			T5	1		T6	1		T7	3
auto[0]	auto[1]	auto[1]	348645	1			T3	2		T5	2		T27	12
auto[0]	auto[1]	auto[2]	342053	1			T3	1		T5	47		T6	1
auto[0]	auto[1]	auto[3]	65829	1			T3	1		T5	292		T27	42
auto[0]	auto[2]	auto[0]	182471	1			T27	2		T31	67		T9	2
auto[0]	auto[2]	auto[1]	18845	1			T3	1		T27	10		T31	4
auto[0]	auto[2]	auto[2]	23261	1			T27	11		T31	12		T40	71
auto[0]	auto[2]	auto[3]	7349	1			T3	1		T27	34		T31	1
auto[0]	auto[3]	auto[0]	3373253	1			T5	9		T6	1		T7	4
auto[0]	auto[3]	auto[1]	337616	1			T5	49		T27	2		T31	3
auto[0]	auto[3]	auto[2]	349406	1			T3	2		T5	44		T6	3
auto[0]	auto[3]	auto[3]	66752	1			T3	3		T5	454		T27	29
auto[1]	auto[0]	auto[0]	9033	1			T121	1		T108	637		T153	130
auto[1]	auto[0]	auto[1]	40168	1			T40	1		T108	2698		T153	569
auto[1]	auto[0]	auto[2]	40068	1			T108	2683		T153	571		T154	355
auto[1]	auto[0]	auto[3]	178859	1			T47	1		T67	1		T108	12008
auto[1]	auto[1]	auto[0]	3619688	1			T48	4		T56	1		T155	4
auto[1]	auto[1]	auto[1]	674242	1			T155	1		T156	2		T67	1
auto[1]	auto[1]	auto[2]	671304	1			T155	2		T156	1		T105	5610
auto[1]	auto[1]	auto[3]	1538628	1			T87	1		T105	527		T106	564
auto[1]	auto[2]	auto[0]	5368	1			T26	1		T108	546		T157	140
auto[1]	auto[2]	auto[1]	23138	1			T108	2399		T157	735		T158	939
auto[1]	auto[2]	auto[2]	35693	1			T108	1747		T153	515		T154	330
auto[1]	auto[2]	auto[3]	160786	1			T108	8231		T153	2313		T154	1469
auto[1]	auto[3]	auto[0]	3613525	1			T48	5		T20	1		T159	4
auto[1]	auto[3]	auto[1]	653522	1			T56	2		T156	1		T105	5576
auto[1]	auto[3]	auto[2]	668224	1			T48	2		T155	2		T156	1
auto[1]	auto[3]	auto[3]	1520435	1			T47	1		T49	2		T156	1