Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	320316781	171498	0	0
ctrl_regwen_rd_A	320316781	3126	0	0
exec_rd_A	320316781	2510	0	0
exec_regwen_rd_A	320316781	2831	0	0
readback_rd_A	320316781	1646	0	0
readback_regwen_rd_A	320316781	1632	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320316781	171498	0	0
T22	46450	0	0	0
T24	17953	1097	0	0
T25	0	1538	0	0
T26	0	3702	0	0
T39	0	3370	0	0
T42	44367	0	0	0
T59	0	6135	0	0
T61	0	953	0	0
T62	0	12514	0	0
T63	0	1431	0	0
T64	0	6453	0	0
T65	0	4332	0	0
T66	1427	0	0	0
T67	61022	0	0	0
T68	17451	0	0	0
T69	5816	0	0	0
T70	3732	0	0	0
T71	102416	0	0	0
T72	27030	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320316781	3126	0	0
T26	118964	314	0	0
T43	8716	0	0	0
T57	0	32	0	0
T74	0	2	0	0
T106	224433	0	0	0
T107	231513	0	0	0
T112	0	124	0	0
T113	0	293	0	0
T114	0	102	0	0
T115	0	105	0	0
T116	0	328	0	0
T117	0	125	0	0
T118	0	546	0	0
T119	4890	0	0	0
T120	17430	0	0	0
T121	56261	0	0	0
T122	290154	0	0	0
T123	811	0	0	0
T124	71061	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320316781	2510	0	0
T26	118964	279	0	0
T43	8716	0	0	0
T57	0	27	0	0
T74	0	10	0	0
T106	224433	0	0	0
T107	231513	0	0	0
T112	0	98	0	0
T113	0	161	0	0
T114	0	63	0	0
T115	0	70	0	0
T116	0	196	0	0
T117	0	105	0	0
T118	0	331	0	0
T119	4890	0	0	0
T120	17430	0	0	0
T121	56261	0	0	0
T122	290154	0	0	0
T123	811	0	0	0
T124	71061	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320316781	2831	0	0
T26	118964	329	0	0
T43	8716	0	0	0
T57	0	45	0	0
T76	0	35	0	0
T106	224433	0	0	0
T107	231513	0	0	0
T112	0	85	0	0
T113	0	300	0	0
T114	0	80	0	0
T115	0	54	0	0
T116	0	331	0	0
T117	0	118	0	0
T118	0	410	0	0
T119	4890	0	0	0
T120	17430	0	0	0
T121	56261	0	0	0
T122	290154	0	0	0
T123	811	0	0	0
T124	71061	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320316781	1646	0	0
T26	118964	292	0	0
T43	8716	0	0	0
T106	224433	0	0	0
T107	231513	0	0	0
T112	0	75	0	0
T113	0	255	0	0
T114	0	75	0	0
T115	0	42	0	0
T116	0	257	0	0
T117	0	106	0	0
T118	0	469	0	0
T119	4890	0	0	0
T120	17430	0	0	0
T121	56261	0	0	0
T122	290154	0	0	0
T123	811	0	0	0
T124	71061	0	0	0
T125	0	9	0	0
T126	0	5	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320316781	1632	0	0
T26	118964	294	0	0
T43	8716	0	0	0
T106	224433	0	0	0
T107	231513	0	0	0
T112	0	104	0	0
T113	0	219	0	0
T114	0	55	0	0
T115	0	61	0	0
T116	0	284	0	0
T117	0	105	0	0
T118	0	411	0	0
T119	4890	0	0	0
T120	17430	0	0	0
T121	56261	0	0	0
T122	290154	0	0	0
T123	811	0	0	0
T124	71061	0	0	0
T127	0	8	0	0
T128	0	16	0	0