Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13941611

1

T2

925

T3

309

T4

17

full_word

56309944

1

T2

66

T3

2947

T4

158

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70251245	1			T2	991		T3	3256		T4	175
auto[TlIntgErrCmd]	113	1			T62	6		T63	1		T64	5
auto[TlIntgErrData]	108	1			T62	7		T63	4		T64	2
auto[TlIntgErrBoth]	89	1			T62	7		T63	5		T64	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32305213

1

T2

369

T3

1648

T4

85

auto[1]

37946342

1

T2

622

T3

1608

T4

90

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6673451	1			T2	367		T3	152		T4	6
auto[TlIntgErrNone]	partial	auto[1]	7267874	1			T2	558		T3	157		T4	11
auto[TlIntgErrNone]	full_word	auto[0]	25631619	1			T2	2		T3	1496		T4	79
auto[TlIntgErrNone]	full_word	auto[1]	30678301	1			T2	64		T3	1451		T4	79
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T62	3		T64	2		T136	4
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T62	3		T63	1		T64	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T138	1		T140	1		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T143	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T62	3		T63	1		T136	2
auto[TlIntgErrData]	partial	auto[1]	59	1			T62	3		T63	3		T64	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T62	1		T136	1		T144	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T64	1		T136	1		T144	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T62	2		T63	3		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T62	4		T63	2		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T62	1		T142	2		T143	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T145	1		T146	1		T147	1