Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	811348	1			T32	415		T34	23		T133	16
auto[1]	11192952	1			T2	324		T3	2		T4	7
auto[2]	683039	1			T4	1		T32	408		T16	1
auto[3]	11076448	1			T2	564		T3	1		T4	5

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15475991	1			T2	7		T3	2		T4	8
auto[1]	2259231	1			T2	59		T4	3		T11	6
auto[2]	2267637	1			T2	91		T4	2		T11	5
auto[3]	3760928	1			T2	731		T3	1		T6	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9323379

1

T2

888

T3

3

T4

13

auto[1]

14440408

1

T30

7

T31

1

T51

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	283124	1			T32	354		T133	14		T162	11
auto[0]	auto[0]	auto[1]	28680	1			T32	28		T34	2		T133	2
auto[0]	auto[0]	auto[2]	28824	1			T32	31		T34	2		T162	71
auto[0]	auto[0]	auto[3]	6435	1			T32	2		T34	19		T162	365
auto[0]	auto[1]	auto[0]	3546304	1			T3	1		T4	4		T11	18
auto[0]	auto[1]	auto[1]	367870	1			T2	2		T4	3		T11	3
auto[0]	auto[1]	auto[2]	359294	1			T2	39		T11	2		T6	5
auto[0]	auto[1]	auto[3]	79243	1			T2	283		T3	1		T6	1
auto[0]	auto[2]	auto[0]	248160	1			T4	1		T32	349		T16	1
auto[0]	auto[2]	auto[1]	25119	1			T32	26		T133	1		T162	53
auto[0]	auto[2]	auto[2]	27157	1			T32	33		T23	2		T34	5
auto[0]	auto[2]	auto[3]	5580	1			T23	2		T34	17		T162	305
auto[0]	auto[3]	auto[0]	3511869	1			T2	7		T3	1		T4	3
auto[0]	auto[3]	auto[1]	354968	1			T2	57		T11	3		T6	3
auto[0]	auto[3]	auto[2]	369067	1			T2	52		T4	2		T11	3
auto[0]	auto[3]	auto[3]	81685	1			T2	448		T31	863		T32	3
auto[1]	auto[0]	auto[0]	15809	1			T39	2		T159	1055		T160	738
auto[1]	auto[0]	auto[1]	69354	1			T159	4729		T160	3438		T161	2208
auto[1]	auto[0]	auto[2]	69044	1			T159	4760		T160	3342		T161	2210
auto[1]	auto[0]	auto[3]	310078	1			T162	1		T159	21147		T160	15262
auto[1]	auto[1]	auto[0]	3928562	1			T51	5		T65	4		T163	5
auto[1]	auto[1]	auto[1]	705675	1			T35	1		T65	1		T72	1
auto[1]	auto[1]	auto[2]	666155	1			T65	1		T90	1		T109	7796
auto[1]	auto[1]	auto[3]	1539849	1			T35	3		T84	1		T109	30612
auto[1]	auto[2]	auto[0]	12469	1			T159	970		T160	669		T161	280
auto[1]	auto[2]	auto[1]	54789	1			T159	4382		T160	3136		T161	1310
auto[1]	auto[2]	auto[2]	56391	1			T159	3183		T160	2299		T161	2503
auto[1]	auto[2]	auto[3]	253374	1			T159	14345		T160	10316		T161	10996
auto[1]	auto[3]	auto[0]	3929694	1			T30	7		T51	3		T103	3
auto[1]	auto[3]	auto[1]	652776	1			T35	2		T103	2		T65	1
auto[1]	auto[3]	auto[2]	691705	1			T103	1		T65	1		T109	6867
auto[1]	auto[3]	auto[3]	1484684	1			T31	1		T35	4		T103	1