Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328011798	185660	0	0
ctrl_regwen_rd_A	328011798	3762	0	0
exec_rd_A	328011798	3573	0	0
exec_regwen_rd_A	328011798	3656	0	0
readback_rd_A	328011798	1686	0	0
readback_regwen_rd_A	328011798	1589	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328011798	185660	0	0
T13	978	0	0	0
T15	25214	0	0	0
T16	21764	1183	0	0
T19	599720	0	0	0
T20	12261	0	0	0
T21	0	5794	0	0
T22	0	1787	0	0
T23	162476	0	0	0
T34	9018	0	0	0
T44	0	2905	0	0
T45	0	4446	0	0
T49	0	5345	0	0
T52	0	5857	0	0
T68	0	1591	0	0
T69	0	1729	0	0
T70	0	3037	0	0
T71	69430	0	0	0
T72	15248	0	0	0
T73	12065	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328011798	3762	0	0
T39	115743	0	0	0
T44	0	169	0	0
T46	0	411	0	0
T68	48030	55	0	0
T115	227726	0	0	0
T119	0	186	0	0
T120	0	136	0	0
T121	0	151	0	0
T122	0	26	0	0
T123	0	127	0	0
T124	0	75	0	0
T125	0	111	0	0
T126	1040	0	0	0
T127	12314	0	0	0
T128	9636	0	0	0
T129	15765	0	0	0
T130	31231	0	0	0
T131	3421	0	0	0
T132	68929	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328011798	3573	0	0
T39	115743	0	0	0
T44	0	131	0	0
T46	0	428	0	0
T68	48030	26	0	0
T115	227726	0	0	0
T119	0	176	0	0
T120	0	96	0	0
T121	0	73	0	0
T122	0	59	0	0
T123	0	89	0	0
T124	0	105	0	0
T125	0	214	0	0
T126	1040	0	0	0
T127	12314	0	0	0
T128	9636	0	0	0
T129	15765	0	0	0
T130	31231	0	0	0
T131	3421	0	0	0
T132	68929	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328011798	3656	0	0
T39	115743	0	0	0
T44	0	141	0	0
T46	0	459	0	0
T68	48030	53	0	0
T115	227726	0	0	0
T119	0	191	0	0
T120	0	105	0	0
T121	0	136	0	0
T122	0	52	0	0
T123	0	102	0	0
T124	0	67	0	0
T125	0	170	0	0
T126	1040	0	0	0
T127	12314	0	0	0
T128	9636	0	0	0
T129	15765	0	0	0
T130	31231	0	0	0
T131	3421	0	0	0
T132	68929	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328011798	1686	0	0
T39	115743	0	0	0
T44	0	140	0	0
T46	0	298	0	0
T68	48030	39	0	0
T115	227726	0	0	0
T119	0	162	0	0
T120	0	127	0	0
T121	0	138	0	0
T122	0	48	0	0
T123	0	81	0	0
T124	0	52	0	0
T125	0	138	0	0
T126	1040	0	0	0
T127	12314	0	0	0
T128	9636	0	0	0
T129	15765	0	0	0
T130	31231	0	0	0
T131	3421	0	0	0
T132	68929	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328011798	1589	0	0
T39	115743	0	0	0
T44	0	194	0	0
T46	0	380	0	0
T68	48030	5	0	0
T115	227726	0	0	0
T119	0	114	0	0
T120	0	75	0	0
T121	0	123	0	0
T122	0	49	0	0
T123	0	60	0	0
T124	0	67	0	0
T125	0	110	0	0
T126	1040	0	0	0
T127	12314	0	0	0
T128	9636	0	0	0
T129	15765	0	0	0
T130	31231	0	0	0
T131	3421	0	0	0
T132	68929	0	0	0