Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14206596

1

T3

2623

T4

857

T5

100

full_word

55116579

1

T1

483

T3

657

T4

55

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69322895	1			T1	483		T3	3280		T4	912
auto[TlIntgErrCmd]	102	1			T46	3		T47	5		T48	4
auto[TlIntgErrData]	94	1			T46	5		T47	1		T48	4
auto[TlIntgErrBoth]	84	1			T46	2		T47	4		T48	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31695385

1

T1

215

T3

1641

T4

348

auto[1]

37627790

1

T1

268

T3

1639

T4

564

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6790147	1			T3	1303		T4	344		T5	55
auto[TlIntgErrNone]	partial	auto[1]	7416192	1			T3	1320		T4	513		T5	45
auto[TlIntgErrNone]	full_word	auto[0]	24905120	1			T1	215		T3	338		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	30211436	1			T1	268		T3	319		T4	51
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T47	2		T48	1		T113	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T46	3		T47	2		T48	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T47	1		T122	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T127	1		T120	1		-	-
auto[TlIntgErrData]	partial	auto[0]	35	1			T46	2		T47	1		T48	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T46	2		T113	1		T122	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T113	1		T123	2		T126	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T46	1		T119	2		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T46	1		T47	2		T48	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T46	1		T47	2		T48	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T128	1		T121	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T124	1		-	-		-	-