Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	796866	1			T3	6		T12	2		T22	281
auto[1]	10581893	1			T1	213		T3	5		T5	483
auto[2]	672963	1			T3	7		T12	1		T22	184
auto[3]	10457229	1			T1	267		T3	5		T5	544

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14335475	1			T1	480		T5	879		T11	2006
auto[1]	2166349	1			T3	2		T5	62		T11	441
auto[2]	2180429	1			T3	3		T5	77		T11	448
auto[3]	3826698	1			T3	18		T5	9		T11	109

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8610025

1

T1

480

T3

23

T5

1026

auto[1]

13898926

1

T5

1

T11

1

T31

9

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	311284	1			T12	2		T22	230		T67	1
auto[0]	auto[0]	auto[1]	32208	1			T22	27		T23	1		T67	5
auto[0]	auto[0]	auto[2]	31932	1			T22	20		T23	1		T67	6
auto[0]	auto[0]	auto[3]	8818	1			T3	6		T22	4		T23	48
auto[0]	auto[1]	auto[0]	3224434	1			T1	213		T5	405		T11	978
auto[0]	auto[1]	auto[1]	340895	1			T5	27		T11	212		T12	1
auto[0]	auto[1]	auto[2]	328063	1			T5	46		T11	219		T12	3
auto[0]	auto[1]	auto[3]	76461	1			T3	5		T5	5		T11	53
auto[0]	auto[2]	auto[0]	271294	1			T22	139		T8	3		T144	175
auto[0]	auto[2]	auto[1]	27871	1			T3	2		T22	16		T8	1
auto[0]	auto[2]	auto[2]	28394	1			T3	1		T12	1		T22	27
auto[0]	auto[2]	auto[3]	6951	1			T3	4		T22	2		T23	29
auto[0]	auto[3]	auto[0]	3181370	1			T1	267		T5	474		T11	1027
auto[0]	auto[3]	auto[1]	323357	1			T5	35		T11	229		T12	1
auto[0]	auto[3]	auto[2]	339357	1			T3	2		T5	30		T11	229
auto[0]	auto[3]	auto[3]	77336	1			T3	3		T5	4		T11	56
auto[1]	auto[0]	auto[0]	13906	1			T132	2		T99	806		T101	1101
auto[1]	auto[0]	auto[1]	61281	1			T144	1		T99	3854		T101	4872
auto[1]	auto[0]	auto[2]	60982	1			T99	3750		T101	4934		T145	629
auto[1]	auto[0]	auto[3]	276455	1			T146	1		T75	1		T99	17174
auto[1]	auto[1]	auto[0]	3664934	1			T31	5		T22	1		T32	2
auto[1]	auto[1]	auto[1]	686036	1			T31	1		T147	1		T86	7428
auto[1]	auto[1]	auto[2]	663520	1			T86	8273		T88	1		T94	8307
auto[1]	auto[1]	auto[3]	1597550	1			T67	1		T86	756		T94	762
auto[1]	auto[2]	auto[0]	10480	1			T132	1		T99	776		T101	1030
auto[1]	auto[2]	auto[1]	45995	1			T99	3511		T101	4699		T148	2
auto[1]	auto[2]	auto[2]	51131	1			T18	1		T99	3209		T101	4090
auto[1]	auto[2]	auto[3]	230847	1			T23	1		T146	2		T99	14381
auto[1]	auto[3]	auto[0]	3657773	1			T11	1		T31	2		T32	1
auto[1]	auto[3]	auto[1]	648706	1			T147	1		T86	8399		T94	8152
auto[1]	auto[3]	auto[2]	677050	1			T5	1		T31	1		T32	3
auto[1]	auto[3]	auto[3]	1552280	1			T86	742		T94	748		T149	6