Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	331882979	197459	0	0
ctrl_regwen_rd_A	331882979	2863	0	0
exec_rd_A	331882979	2694	0	0
exec_regwen_rd_A	331882979	2762	0	0
readback_rd_A	331882979	1440	0	0
readback_regwen_rd_A	331882979	1322	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331882979	197459	0	0
T7	68712	0	0	0
T13	1040	0	0	0
T15	24549	0	0	0
T17	433257	0	0	0
T19	0	5375	0	0
T22	98723	3702	0	0
T23	14688	0	0	0
T24	0	2134	0	0
T25	0	1733	0	0
T26	2162	0	0	0
T32	11081	0	0	0
T33	33853	0	0	0
T40	0	1069	0	0
T41	0	1139	0	0
T42	0	6115	0	0
T51	0	1508	0	0
T54	0	2429	0	0
T55	0	9959	0	0
T56	51418	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331882979	2863	0	0
T18	757305	0	0	0
T40	17722	43	0	0
T44	9529	0	0	0
T46	0	16	0	0
T57	40193	0	0	0
T58	0	6	0	0
T61	0	33	0	0
T88	12832	0	0	0
T89	53302	0	0	0
T90	2442	0	0	0
T104	0	197	0	0
T105	0	432	0	0
T106	0	96	0	0
T107	0	398	0	0
T108	0	324	0	0
T109	0	9	0	0
T110	338312	0	0	0
T111	38834	0	0	0
T112	12915	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331882979	2694	0	0
T18	757305	0	0	0
T40	17722	31	0	0
T44	9529	0	0	0
T46	0	39	0	0
T57	40193	0	0	0
T58	0	7	0	0
T61	0	28	0	0
T88	12832	0	0	0
T89	53302	0	0	0
T90	2442	0	0	0
T104	0	162	0	0
T105	0	352	0	0
T106	0	68	0	0
T107	0	367	0	0
T108	0	349	0	0
T109	0	22	0	0
T110	338312	0	0	0
T111	38834	0	0	0
T112	12915	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331882979	2762	0	0
T18	757305	0	0	0
T40	17722	61	0	0
T44	9529	0	0	0
T46	0	26	0	0
T57	40193	0	0	0
T58	0	3	0	0
T61	0	47	0	0
T88	12832	0	0	0
T89	53302	0	0	0
T90	2442	0	0	0
T104	0	165	0	0
T105	0	418	0	0
T106	0	89	0	0
T107	0	483	0	0
T108	0	388	0	0
T109	0	11	0	0
T110	338312	0	0	0
T111	38834	0	0	0
T112	12915	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331882979	1440	0	0
T18	757305	0	0	0
T40	17722	7	0	0
T44	9529	0	0	0
T57	40193	0	0	0
T88	12832	0	0	0
T89	53302	0	0	0
T90	2442	0	0	0
T104	0	165	0	0
T105	0	311	0	0
T106	0	117	0	0
T107	0	326	0	0
T108	0	346	0	0
T109	0	25	0	0
T110	338312	0	0	0
T111	38834	0	0	0
T112	12915	0	0	0
T113	0	7	0	0
T114	0	16	0	0
T115	0	1	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331882979	1322	0	0
T18	757305	0	0	0
T40	17722	20	0	0
T44	9529	0	0	0
T57	40193	0	0	0
T88	12832	0	0	0
T89	53302	0	0	0
T90	2442	0	0	0
T104	0	123	0	0
T105	0	376	0	0
T106	0	82	0	0
T107	0	285	0	0
T108	0	275	0	0
T109	0	4	0	0
T110	338312	0	0	0
T111	38834	0	0	0
T112	12915	0	0	0
T114	0	22	0	0
T116	0	1	0	0
T117	0	3	0	0