Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13670358

1

T2

58

T3

130

T4

53

full_word

56072885

1

T2

552

T3

635

T4

578

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69742913	1			T2	610		T3	765		T4	631
auto[TlIntgErrCmd]	115	1			T50	8		T51	2		T52	11
auto[TlIntgErrData]	114	1			T50	5		T51	6		T52	6
auto[TlIntgErrBoth]	101	1			T50	7		T51	2		T52	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31857104

1

T2

289

T3

398

T4

312

auto[1]

37886139

1

T2

321

T3

367

T4

319

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6514543	1			T2	31		T3	62		T4	25
auto[TlIntgErrNone]	partial	auto[1]	7155520	1			T2	27		T3	68		T4	28
auto[TlIntgErrNone]	full_word	auto[0]	25342409	1			T2	258		T3	336		T4	287
auto[TlIntgErrNone]	full_word	auto[1]	30730441	1			T2	294		T3	299		T4	291
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T50	2		T52	2		T121	4
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T50	6		T51	2		T52	9
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T122	2		T123	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T51	4		T52	3		T122	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T50	5		T51	2		T52	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T125	1		T126	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	13	1			T52	1		T121	2		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T50	3		T51	2		T52	1
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T50	4		T52	2		T121	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T125	1		T126	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T122	1		T128	1		T127	2