Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	611480	1			T32	1		T38	1		T40	536
auto[1]	10298592	1			T3	397		T4	260		T9	1175
auto[2]	490469	1			T4	1		T32	3		T38	3
auto[3]	10177107	1			T3	366		T4	281		T9	1199

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14108778	1			T3	516		T4	465		T9	2374
auto[1]	2044351	1			T3	117		T4	39		T21	502
auto[2]	2065303	1			T3	110		T4	33		T21	457
auto[3]	3359216	1			T3	20		T4	5		T21	123

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8058821

1

T3

763

T4

542

T9

2374

auto[1]

13518827

1

T21

4

T29

1

T49

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	198862	1			T32	1		T40	448		T65	5
auto[0]	auto[0]	auto[1]	20052	1			T40	41		T148	34		T81	2
auto[0]	auto[0]	auto[2]	20254	1			T40	45		T148	48		T81	4
auto[0]	auto[0]	auto[3]	4831	1			T38	1		T41	16		T148	4
auto[0]	auto[1]	auto[0]	3124532	1			T3	274		T4	226		T9	1175
auto[0]	auto[1]	auto[1]	322586	1			T3	61		T4	16		T21	266
auto[0]	auto[1]	auto[2]	314929	1			T3	54		T4	15		T21	220
auto[0]	auto[1]	auto[3]	66895	1			T3	8		T4	3		T21	67
auto[0]	auto[2]	auto[0]	157503	1			T4	1		T32	2		T40	251
auto[0]	auto[2]	auto[1]	16007	1			T40	21		T65	1		T148	26
auto[0]	auto[2]	auto[2]	22646	1			T32	1		T40	45		T148	42
auto[0]	auto[2]	auto[3]	4593	1			T38	3		T40	5		T41	11
auto[0]	auto[3]	auto[0]	3081214	1			T3	242		T4	238		T9	1199
auto[0]	auto[3]	auto[1]	310993	1			T3	56		T4	23		T21	236
auto[0]	auto[3]	auto[2]	324593	1			T3	56		T4	18		T21	235
auto[0]	auto[3]	auto[3]	68331	1			T3	12		T4	2		T21	56
auto[1]	auto[0]	auto[0]	12131	1			T40	2		T148	1		T146	351
auto[1]	auto[0]	auto[1]	54479	1			T148	1		T146	1665		T147	618
auto[1]	auto[0]	auto[2]	54726	1			T146	1632		T147	634		T149	4105
auto[1]	auto[0]	auto[3]	246145	1			T148	1		T81	3		T146	7131
auto[1]	auto[1]	auto[0]	3766097	1			T150	2		T56	4		T76	6
auto[1]	auto[1]	auto[1]	655670	1			T151	1		T152	1		T98	4072
auto[1]	auto[1]	auto[2]	637979	1			T21	1		T153	2		T98	4041
auto[1]	auto[1]	auto[3]	1409904	1			T49	1		T81	1		T98	365
auto[1]	auto[2]	auto[0]	8908	1			T40	1		T146	197		T149	910
auto[1]	auto[2]	auto[1]	39680	1			T146	948		T149	3827		T154	3789
auto[1]	auto[2]	auto[2]	43929	1			T146	1571		T147	603		T149	3569
auto[1]	auto[2]	auto[3]	197203	1			T146	6937		T147	2652		T149	15901
auto[1]	auto[3]	auto[0]	3759531	1			T21	2		T56	2		T76	3
auto[1]	auto[3]	auto[1]	624884	1			T76	1		T152	1		T153	2
auto[1]	auto[3]	auto[2]	646247	1			T21	1		T151	1		T152	1
auto[1]	auto[3]	auto[3]	1361314	1			T29	1		T66	1		T98	373